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path: root/src/soc/intel
AgeCommit message (Expand)Author
2015-03-09broadwell: enable PCIe endpoint CLK power managementKane Chen
2015-03-09coreboot: fix munged license textAaron Durbin
2015-03-05fsp_baytrail: Add I2C driverWerner Zeh
2015-03-05fsp_baytrail: Add new microcode for Bay Trail MWerner Zeh
2015-02-27x86: Fix pointer arithmetic regressions from MMIO changesKevin Paul Herbert
2015-02-25soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER`Paul Menzel
2015-02-25intel/broadwell: free local heap objectPatrick Georgi
2015-02-24soc/fsp_baytrail: Fix use of microcode-related Kconfig variablesAlexandru Gagniuc
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
2015-02-13fsp_baytrail: Add macros to define 20K pull-up and downWerner Zeh
2015-02-10Baytrail_fsp: Make ME path configurable in menuconfigWerner Zeh
2015-02-09fsp_baytrail: Get FSP reserved memory from the FSP HOB listMartin Roth
2015-02-09Intel FSP platforms: Fix timestampsKyösti Mälkki
2015-02-06FSP & CBMEM: Fix broken cbmem CAR transition.Martin Roth
2015-01-27CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki
2015-01-27CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEMKyösti Mälkki
2015-01-27CBMEM: Move cbmemc_reinit()Kyösti Mälkki
2015-01-27vboot2: add verstageStefan Reinauer
2015-01-16baytrail: there is a chance that USBPHY_COMPBG is set to 0Kane Chen
2015-01-16baytrail: use the setting in devicetree.cb to config USBPHY_COMPBGKane Chen
2015-01-14baytrail broadwell: Use timestamps internal stashKyösti Mälkki
2015-01-13soc/intel/fsp_baytrail/gpio.c: Silence unused variable warningEdward O'Callaghan
2015-01-12soc/intel/broadwell/me.c: Prevent unused function warningEdward O'Callaghan
2015-01-12soc/intel/broadwell/spi_loading.c: Remove dead codeEdward O'Callaghan
2015-01-06broadwell: Use correct include file for console functionsStefan Reinauer
2015-01-06Revert "Re-factor 'to_flash_offset()' into 'spi_flash.h'"Kyösti Mälkki
2015-01-06doxygen fixes: change @var to @param varMartin Roth
2015-01-06Re-factor 'to_flash_offset()' into 'spi_flash.h'Edward O'Callaghan
2015-01-05timestamps: Switch from tsc_t to uint64_tStefan Reinauer
2014-12-31broadwell: Hook into the build systemDuncan Laurie
2014-12-31broadwell: Preparations for buildingMarc Jones
2014-12-31baytrail: add more gpio init macrosKane Chen
2014-12-30baytrail: Add defines and functions for GPNCOREKein Yuan
2014-12-28intel baytrail broadwell: Include microcode updatesKyösti Mälkki
2014-12-19fsp_baytrail: Initialize LPC pads in bootblock for port 80Martin Roth
2014-12-19fsp_baytrail: Remove GPIO_NC1 #defineMartin Roth
2014-12-19baytrail SOCs: Add missing comma in gpio.hMartin Roth
2014-12-17baytrail: initialize backlight PWM frequencyAaron Durbin
2014-12-17x86: Initialize SPI controller explicitly during PCH initDavid Hendricks
2014-12-17fsp_baytrail: Add code to read GPIOs in romstageMartin Roth
2014-12-16CBMEM console: Fix boards with BROKEN_CAR_MIGRATEKyösti Mälkki
2014-12-16Intel FSP: Move to DYNAMIC_CBMEMKyösti Mälkki
2014-12-09spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions.Gabe Black
2014-12-09spi: Remove the spi_set_speed and spi_cs_is_valid functions.Gabe Black
2014-12-09fsp platfoms: add prototype & consolidate main entry-pointMartin Roth
2014-12-08intel/baytrail: Spelling fixesMartin Roth
2014-12-08intel/fsp_baytrail: Spelling fixesMartin Roth
2014-12-08intel/broadwell: Spelling fixesMartin Roth
2014-12-05fsp_baytrail: Update function disable codeMartin Roth
2014-12-05fsp_baytrail: Kconfig update for Gold 3 FSPMartin Roth
2014-12-05fsp_baytrail: Update microcode for Gold 3 FSP releaseMartin Roth
2014-12-05FSP platform microcode: Update to remove Kconfig variableMartin Roth
2014-12-05fsp_baytrail: remove register option for TSEG sizeMartin Roth
2014-12-05fsp_baytrail: update printk to use FSP_INFO_LEVELMartin Roth
2014-12-05fsp_baytrail: update for UPD_DEVICE_CHECK macroMartin Roth
2014-12-05fsp_baytrail: update to add the UPD_MEMDOWN_CHECK macroMartin Roth
2014-12-05fsp_baytrail: update for UPD_SPD_CHECK macroMartin Roth
2014-12-05fsp_baytrail: update to add the UPD_DEFAULT_CHECK macroMartin Roth
2014-12-02Replace hlt with halt()Patrick Georgi
2014-12-01Mark non-executable files non-executablePatrick Georgi
2014-11-30Replace hlt() loops with halt()Patrick Georgi
2014-11-28ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki
2014-11-25intel: Remove IRQ1 from possible PIRQ assignemnt.Vladimir Serbinenko
2014-11-24intel/fsp_baytrail: add new CPUID for Baytrail I step D0Herve ELter
2014-11-21intel/fsp_baytrail: add Gold3 FSP supportYork Yang
2014-11-20Replace includes of build.h with version.hKyösti Mälkki
2014-11-19broadwell: move to per-device ACPI.Vladimir Serbinenko
2014-11-19fsp_baytrail: Fix ACPI 'Object is not referenced' warningsMartin Roth
2014-11-19fsp_baytrail: Update chip.h UPD entries to match names in fspvpd.hMartin Roth
2014-11-18baytrail: fix range checkPatrick Georgi
2014-11-13intel: use crosscompiler readelf, instead of globalPatrick Georgi
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
2014-11-08intel: Use 'FORCEWAKE_ACK_HSW' define over '0x130044'Edward O'Callaghan
2014-11-04Redundant addr '&' operator on func ptr's in struct initiatorEdward O'Callaghan
2014-11-01{cpu,soc}: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
2014-10-28baytrail: Remove unused devicetree fieldsShawn Nematbakhsh
2014-10-28baytrail: gfx: Don't configure hotplug + backlight registersShawn Nematbakhsh
2014-10-28Baytrail/dptf: Always return 0 in TCPU._PPCKein Yuan
2014-10-28baytrail: handle MRC being an ELF fileAaron Durbin
2014-10-28baytrail: Configure MSR for 2-core and 4-core P-state configutationDuncan Laurie
2014-10-28baytrail: move cache-as-ram base address to 0xfe000000Aaron Durbin
2014-10-28baytrail: romstage: Add function to check SW WP status for vbootShawn Nematbakhsh
2014-10-22reg_script: default to n for ARCH_X86Isaac Christensen
2014-10-22cmos: Rename the CMOS related functions.Gabe Black
2014-10-22broadwell: Update Haswell and Broadwell E0 microcodeDuncan Laurie
2014-10-22broadwell: Update microcodeDuncan Laurie
2014-10-22broadwell: ACPI, romstage, and other updatesDuncan Laurie
2014-10-22broadwell: Update D0 microcode to FFFF000EDuncan Laurie
2014-10-22broadwell: Update microcode for supported CPUsDuncan Laurie
2014-10-22broadwell: add new intel SOCDuncan Laurie
2014-10-22baytrail: Move HDA verb table to Intel SOC common directoryDuncan Laurie
2014-10-22baytrail: Move MRC cache code to a common directoryDuncan Laurie
2014-10-22baytrail/rambi: S3 support and other updatesKein Yuan
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
2014-10-19haswell baytrail: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
2014-10-14intel/fsp_baytrail: Add padding so device_nvs location matches ACPIScott Radcliffe
2014-10-14baytrail: Add padding to the end of device_nvs to match ACPIScott Radcliffe
2014-10-14intel/fsp_baytrail: Clear the GNVS area prior to fillingScott Radcliffe
2014-10-09intel/fsp_baytrail: Include header for "southcluster_smm_save_gpio_route"Kayalvizhi Dhandapani
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