coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-12-21	soc/intel/xeon_sp/skx: Properly set up MTRR's	Arthur Heymans
2020-11-24	soc/intel/xeon_sp: Enable SMI handler	Rocky Phagura
2020-10-30	soc/intel/xeon_sp: Move read_msr_ppin() to common util.c	Marc Jones
2020-10-29	soc/intel/xeon_sp: Move function debug macros	Marc Jones
2020-10-23	soc/intel/xeon_sp/skx: Add missing includes	Angel Pons
2020-09-21	src/soc/intel: Drop unneeded empty lines	Elyes HAOUAS
2020-07-04	soc/intel/xeon_sp: Add read CPU PPIN MSR function	Johnny Lin
2020-06-16	sb,soc/intel: Replace smm_southbridge_enable_smi()	Kyösti Mälkki
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-03-26	soc/intel/xeon_sp: Refactor code to allow for additional CPUs types	Andrey Petrov