| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-12-06 | soc/intel/xeon_sp: Read ioapic configuration from hardware | Arthur Heymans |
| 2022-07-15 | soc/intel/xeon_sp: Make gsi_bases platform independent | Christian Walter |
| 2021-11-03 | cpu/x86/Kconfig: Remove unused CPU_ADDR_BITS | Arthur Heymans |
| 2021-06-28 | xeon_sp/{cpx,skx}: Add config IFD_CHIPSET 'lbg' | Johnny Lin |
| 2021-01-28 | arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limits | Kyösti Mälkki |
| 2020-11-24 | soc/intel/xeon_sp: Enable SMI handler | Rocky Phagura |
| 2020-10-09 | soc/intel/xeon_sp: Set CPU_ADDR_BITS to 46 for SKX and CPX | Christian Walter |
| 2020-05-26 | soc/intel/xeon_sp: select UDK_2017_binding | Jonathan Zhang |
| 2020-05-18 | src: Remove leading blank lines from SPDX header | Elyes HAOUAS |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-03-26 | soc/intel/xeon_sp: Refactor code to allow for additional CPUs types | Andrey Petrov |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |