coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-10-30	soc/intel/xeon_sp: Move read_msr_ppin() to common util.c	Marc Jones
2020-10-29	soc/intel/xeon_sp: Move function debug macros	Marc Jones
2020-10-08	soc/intel/xeon_sp/cpx: Add locking of IA32_FEATURE_CONTROL and VMX	Christian Walter
2020-09-21	src/soc/intel: Drop unneeded empty lines	Elyes HAOUAS
2020-08-18	xeon_sp/cpx: Enable ACPI P-state support	Jingle Hsu
2020-08-13	soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processor	Jonathan Zhang
2020-08-07	xeon_sp/cpx: Enable HWP Intel Speed Shift	Johnny Lin
2020-07-04	soc/intel/xeon_sp: Add read CPU PPIN MSR function	Johnny Lin
2020-06-16	sb,soc/intel: Replace smm_southbridge_enable_smi()	Kyösti Mälkki
2020-06-06	soc/intel/xeon_sp/cpx: set up cpus	Jonathan Zhang
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-02	acpi: Move ACPI table support out of arch/x86 (3/5)	Furquan Shaikh
2020-04-24	soc/intel/xeon_sp/cpx: Calculate number of threads based on sockets	Andrey Petrov
2020-04-24	soc/intel/xeon_sp/cpx: Work around FSP-M issues	Andrey Petrov
2020-04-04	soc/intel/xeon_sp/cpx: Add multi-core init	Andrey Petrov