coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-10-09	soc/intel/xeon_sp: Set CPU_ADDR_BITS to 46 for SKX and CPX	Christian Walter
2020-08-20	soc/intel/xeon_sp/cpx/Kconfig: Relocate 'select CACHE_MRC_SETTINGS'	Elyes HAOUAS
2020-08-18	xeon_sp/cpx: Enable ACPI P-state support	Jingle Hsu
2020-08-03	soc/intel/xeon_sp/cpx: configure STACK_SIZE	Jonathan Zhang
2020-08-03	soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2	Jonathan Zhang
2020-07-31	soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS	Jonathan Zhang
2020-05-26	soc/intel/xeon_sp: select UDK_2017_binding	Jonathan Zhang
2020-05-18	src: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-01	soc/intel/xeon_sp/cpx: Enable common P2SB	Andrey Petrov
2020-04-24	soc/intel/xeon_sp/cpx: Bump MAX_CPUS	Andrey Petrov
2020-04-24	soc/intel/xeon_sp/cpx: Work around FSP-M issues	Andrey Petrov
2020-03-26	soc/intel/xeon_sp: Add basic Cooperlake-SP support	Andrey Petrov