coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-06-21	security/intel/cbnt: Add logging	Arthur Heymans
2021-05-20	soc/intel/xeon_sp: Remove superfluous printk	Arthur Heymans
2020-11-22	soc/intel/xeon_sp: Work around FSP-T not respecting its own API	Arthur Heymans
2020-11-02	soc/intel/xeon_sp/bootblock.c: Report the FSP-T output	Arthur Heymans
2020-06-02	vendorcode/intel/fsp/fsp2_0/cpx_sp: update to FSP WW20 release	Jonathan Zhang
2020-06-02	soc/intel/xeon_sp: Early programming of ACPI bar	Rocky Phagura
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-03-26	soc/intel/xeon_sp: Configure P2SB BAR in bootblock	Andrey Petrov
2020-03-26	soc/intel/xeon_sp: Refactor code to allow for additional CPUs types	Andrey Petrov