coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-11-05	soc/intel/xeon_sp: Use common cpu/intel romstage entry	Arthur Heymans
2020-11-04	soc/intel/xeon_sp: Add a smm_region function	Arthur Heymans
2020-10-30	soc/intel/xeon_xp: Combine cpx and skx acpi.c	Marc Jones
2020-10-30	soc/intel/xeon_sp: Move common chip.c code	Marc Jones
2020-10-28	src/soc/intel/xeon_sp: Fill in the cache information in SMBIOS type 7	Morgan Jang
2020-10-22	soc/intel/xeon_sp: Move common northbridge ACPI to nb_acpi.c	Marc Jones
2020-09-21	soc/intel/xeon_sp: Enable PMC support	Rocky Phagura
2020-07-12	soc/intel/xeon_sp: Add RTC failure checking	Jingle Hsu
2020-06-02	soc/intel/xeon_sp: Early programming of ACPI bar	Rocky Phagura
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-10	src: Replace remaining GPLv2 long form headers with SPDX header	Elyes HAOUAS
2020-04-07	soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver	Maxim Polyakov
2020-03-26	soc/intel/xeon_sp: Add basic Cooperlake-SP support	Andrey Petrov
2020-03-26	soc/intel/xeon_sp: Refactor code to allow for additional CPUs types	Andrey Petrov
2020-03-25	soc/intel/xeon_sp: Enable LPC generic IO decode range	Johnny Lin
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-06	soc/intel: Add Intel Xeon Scalable Processor support	Jonathan Zhang