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2023-06-15soc/intel: Add max memory speed into dimm infoEric Lai
Add MaximumMemoryClockSpeed if FSP have it, otherwise pass 0. TEST=check dmidecode dump the max speed. Handle 0x000C, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 16 GB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR5 Type Detail: Unknown Synchronous Speed: 5600 MT/s Manufacturer: Micron Serial Number: 3f064d84 Asset Tag: Channel-0-DIMM-0-AssetTag Part Number: MTC8C1084S1SC56BG1 Rank: 1 Configured Memory Speed: 5200 MT/s Minimum Voltage: 1.1 V Maximum Voltage: 1.1 V Configured Voltage: 1.1 V Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75810 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-01soc/intel/tgl: Unhide PMC, IOM ACPI devices from OSMatt DeVillier
These were hidden because no Windows drivers existed, but now that they do, the ACPI devices need to be visible in order for the drivers to properly attach. TEST=build google/drobit, boot Windows, verify Windows drivers correctly attach to PCM/IOM devices. Change-Id: I1520a71e318674baa234fc6a2126d1d17933d983 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-20soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORTSean Rhodes
Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is only used on `starlabs/starbook` which selects D3COLD_SUPPORT so the UPDs will not change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20soc/intel/tigerlake: Replace SOC_INTEL_TIGERLAKE_S3 with D3COLD_SUPPORTSean Rhodes
The Kconfig option SOC_INTEL_TIGERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support. Remove it, and instead use D3COLD_SUPPORT so it's clear what the option is doing. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74405 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15soc/intel/tigerlake: Enable early caching of RAMTOP regionLean Sheng Tan
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I3b68d13aa414e69c0a80122021e6755352db32fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73738 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"Michael Niewöhner
This reverts commit 6bfca1b689e48be4f72e8fa401f3558d845fc282. Reason for revert: dependency for revert CB:73903 Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12Revert "soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol"Michael Niewöhner
This reverts commit fd4ad29f1824ad5d8df67f3e30d3908d24cbd8a4. Reason for revert: dependency for revert CB:73903 Change-Id: I5ed5e3e267032d62d65aef7fb246a075dccc9cf6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-15soc/intel/tigerlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I97c8c07db9b44aa89b433e7962ec77c8501ecaa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-01soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbolSean Rhodes
Replace the SOC_INTEL_TIGERLAKE_S3 and SOC_INTEL_ALDERLAKE_S3 with the D3COLD_SUPPORT symbol, as it allows for more granular control. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I07e8c84e5ad8f390bfbac017dd23736e7a6ced9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-24soc/intel/tgl: Select CSE defined ME spec version for tigerlakeDinesh Gehlot
Tigerlake based SoCs uses Intel's Management Engine (ME), version 15. This patch selects ME 15 specification defined at common code and removes tigerlake SoC specific ME code and data structures. BUG=b:260309647 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: If4fbfd7c591794ed945c1e9e8487a9e9723c7551 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73138 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-23soc/intel: Use common codeflow for MP initArthur Heymans
This fixes MP init on xeon_sp SoCs which was broken by 69cd729 (mb/*: Remove lapic from devicetree). Alderlake cpu code was linked in romstage but unused so drop it. Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-20soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORTSean Rhodes
Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive` so their configurations are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-09Revert "device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT"Felix Singer
This reverts commit d6e04aa00bc5a8912a041a569eb57f6962d1119a. Reason for revert: Breaks master. Change-Id: If7daeaaffe3f9ae9f5e2fbecef5817b9b62827d3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72917 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-08device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORTSean Rhodes
Add NO_S0IX_SUPPORT for boards that do not support, or do not want to support S0IX. As all the boards in the tree that do this, don't support D3Cold, add D3COLD_SUPPORT that defaults to `n` when NO_S0IX_SUPPORT is selected to disable D3Cold support. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04abc7efe2db06ae6daba9e09835441b62ee44f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-08soc/intel/{tgl,adl}/acpi: Unify the way D3Cold is enabledSean Rhodes
Both Alder Lake and Tiger Lake have Kconfig options for S3, which disables support for D3Cold. Unify these so that they are easier to compare. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6eaba99e5483053a91ca20df2b7788edac5d65b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72798 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04soc/intel/tgl: Move ME FSR structures to pertinent headerDinesh Gehlot
This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ib96fcb86fd2c3fe16f23c8f038f4930a832a5b01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/intel/{adl,mtl,tgl}: change selection for ↵Matt DeVillier
DEFAULT_SOFTWARE_CONNECTION_MANAGER Needs to be selected for ChromeOS mainboards even for non-ChromeOS builds, else Thunderbolt/USB4 doesn't work under Windows (and likely Linux as well). TEST=build/boot Windows on drobit/banshee, verify TB functional Change-Id: Iee3f99840f0c6cc384d9fdef6dff55bcbfc0380f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72140 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/intel/*/include/soc/gpio.h: Add "IWYU pragma: export" commentElyes Haouas
Change-Id: If44a07503470f57037b59d03eea830703a3c604a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72100 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/intel: Remove unused <stddef.h>Elyes Haouas
Change-Id: I8432d799c9bf23058b7b903bb07f6c2b4308eeba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72103 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/intel/tigerlake: Fix incorrect `prev_sleep_state` issueSubrata Banik
The patch fixes indication of incorrect `prev_sleep_state` on the next boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power failure. As a result, every early warm/global reset is considered as power failure after looking into the PMC MMIO CON-A register alone (as ignoring the ACPI PM_CTRL.WAK_STS bit). As per the code comment this code logic is expected to check the power failure reason if PCH doesn't set the WAK_STS while waking from G3 state. TEST=Able to build and boot google/volteer. Without this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 5 With this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 0`. It matches with the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0e48b110826f16d13d18c138fce03a56c85b9d1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71985 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-18soc/intel/tigerlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes alphabetic ordering of included headers. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I12497d46e58aae41ec8dcb5d567267579dc12fc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72041 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11device/Kconfig: Fix selection of software connection managerMartin Roth
The patch that introduced the selection of software connection manager, CB:64561 - 060df17f1d (soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM) added a default to enable the software configuration manager directly in the choice. This leads to warnings when running make menuconfig: src/soc/intel/alderlake/Kconfig:439: warning: defaults for choice values not supported src/soc/intel/meteorlake/Kconfig:337: warning: defaults for choice values not supported src/soc/intel/tigerlake/Kconfig:299: warning: defaults for choice values not supported I'm not sure why the Kconfig linter didn't catch this, but this issue is currently breaking the build for me. This patch fixes it so that instead of setting the default directly, a new Kconfig value is selected that then sets the default correctly. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I674046a93af8f7c2f3003900804deefa89dae295 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71776 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-01-11soc/intel/{alderlake,tigerlake}: Fix typo in gpio_defs.hJakub Czapiga
Alder Lake and Tiger Lake had unnecessary lower-case 'i' in GPP_C0_IRQ define name. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ida892b00e5a28544950cb9863d0ff2408a514576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71819 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-01-08soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCMSean Rhodes
Software Connection Manager doesn't work with Linux 5.13 or later, resulting in TBT ports timing out. Not advertising this results in Firmware Connection Manager being used and TBT works correctly. Add Kconfig options to chose between SCM (Software Connection Manager) and FCM (Firmware Connection Manager). FCM is primary, as it's more compatible save for ChromeOS devices as ChromeOS uses SCM. Linux patch: torvalds/linux@c6da62a c6da62a219d028de10f2e22e93a34c7ee2b88d03 Tested with StarBook Mk VI (i7-1260P). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-04soc/intel: Create common function to check PCH slotKapil Porwal
BUG=none TEST=Build and boot to google/taniks. Check dmesg and make sure that there is no regression. Also confirm that there is no change in ACPI _PRT and IO-APCI interrupt assignment. IO-APIC interrupts before and after this patch: 1: IO-APIC 1-edge i8042 8: IO-APIC 8-edge rtc0 9: IO-APIC 9-fasteoi acpi 14: IO-APIC 14-fasteoi INTC1055:00 23: IO-APIC 23-fasteoi idma64.5, ttyS0 37: IO-APIC 37-fasteoi idma64.0, i2c_designware.0 38: IO-APIC 38-fasteoi idma64.1, i2c_designware.1 40: IO-APIC 40-fasteoi idma64.2, i2c_designware.2 41: IO-APIC 41-fasteoi idma64.3, i2c_designware.3 42: IO-APIC 42-fasteoi idma64.4, i2c_designware.4 45: IO-APIC 45-fasteoi idma64.6, pxa2xx-spi.6 77: IO-APIC 77-edge cr50_i2c 100: IO-APIC 100-fasteoi ELAN0000:00 103: IO-APIC 103-fasteoi chromeos-ec _PRT before and after this patch: Package (0x04) ==> 0x0001FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0002FFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x0004FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0005FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x0007FFFF, 0x00, 0x00, 0x00000013 Package (0x04) ==> 0x0007FFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x0007FFFF, 0x02, 0x00, 0x00000015 Package (0x04) ==> 0x0007FFFF, 0x03, 0x00, 0x00000016 Package (0x04) ==> 0x0008FFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x000DFFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x000DFFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0010FFFF, 0x00, 0x00, 0x00000018 Package (0x04) ==> 0x0010FFFF, 0x01, 0x00, 0x00000019 Package (0x04) ==> 0x0010FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0010FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0011FFFF, 0x00, 0x00, 0x0000001A Package (0x04) ==> 0x0011FFFF, 0x01, 0x00, 0x0000001B Package (0x04) ==> 0x0011FFFF, 0x02, 0x00, 0x0000001C Package (0x04) ==> 0x0011FFFF, 0x03, 0x00, 0x0000001D Package (0x04) ==> 0x0012FFFF, 0x00, 0x00, 0x0000001E Package (0x04) ==> 0x0012FFFF, 0x01, 0x00, 0x0000001F Package (0x04) ==> 0x0012FFFF, 0x02, 0x00, 0x00000016 Package (0x04) ==> 0x0013FFFF, 0x00, 0x00, 0x00000020 Package (0x04) ==> 0x0013FFFF, 0x01, 0x00, 0x00000021 Package (0x04) ==> 0x0013FFFF, 0x02, 0x00, 0x00000022 Package (0x04) ==> 0x0013FFFF, 0x03, 0x00, 0x00000023 Package (0x04) ==> 0x0014FFFF, 0x01, 0x00, 0x00000017 Package (0x04) ==> 0x0014FFFF, 0x00, 0x00, 0x00000024 Package (0x04) ==> 0x0014FFFF, 0x02, 0x00, 0x00000011 Package (0x04) ==> 0x0015FFFF, 0x00, 0x00, 0x00000025 Package (0x04) ==> 0x0015FFFF, 0x01, 0x00, 0x00000026 Package (0x04) ==> 0x0015FFFF, 0x02, 0x00, 0x00000027 Package (0x04) ==> 0x0015FFFF, 0x03, 0x00, 0x00000028 Package (0x04) ==> 0x0016FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0016FFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0016FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0016FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0017FFFF, 0x00, 0x00, 0x00000016 Package (0x04) ==> 0x0019FFFF, 0x00, 0x00, 0x00000029 Package (0x04) ==> 0x0019FFFF, 0x01, 0x00, 0x0000002A Package (0x04) ==> 0x0019FFFF, 0x02, 0x00, 0x0000002B Package (0x04) ==> 0x001CFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001CFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001CFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001CFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001DFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001DFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001DFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001DFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001EFFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x001EFFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x001EFFFF, 0x02, 0x00, 0x0000002C Package (0x04) ==> 0x001EFFFF, 0x03, 0x00, 0x0000002D Package (0x04) ==> 0x001FFFFF, 0x01, 0x00, 0x00000016 Package (0x04) ==> 0x001FFFFF, 0x02, 0x00, 0x00000017 Package (0x04) ==> 0x001FFFFF, 0x03, 0x00, 0x00000014 Package (0x04) ==> 0x001FFFFF, 0x00, 0x00, 0x00000015 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib4fc850228b7ddbf84e2feb2433adff5e4002033 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71236 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23soc/intel: Drop SoC specific DPTF implementationSubrata Banik
This patch drops the SoC specific implementation as DPTF driver can now fillin those platform specific data using SoC specific macros. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If65976f15374ba2410b537b1646ce466ba02969b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel: Set `use_eisa_hids` based on `DPTF_USE_EISA_HID` configSubrata Banik
This patch avoids hardcoding to the `use_eisa_hids` variable instead relying on the SoC config to choose if the SoC platform supports EISA HID. If any SoC platform has the support then the `use_eisa_hids` variable would be set to `true` based on the selection of `DPTF_USE_EISA_HID` config. Note: Prior to Tiger Lake, all DPTF devices used 7-character EISA IDs. If selected, the 7-character _HIDs will be emitted, otherwise, it will use the "new" style, which are regular 8-character _HIDs. Ideally, the platform prior to Tiger Lake would set `use_eisa_hids` to `true` and platform posts that would set `use_eisa_hids` to `false`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I869bebc8e17c1e65979ca3431308d69771a34fa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71110 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/tigerlake: Move DPTF ACPI Device IDs into header fileSubrata Banik
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. TEST=Able to build and boot Google/Volteer. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I111fa9b2672ad01268bb2620b47a53a7a5b00f3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71107 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22drivers/intel/dptf: Add `soc_` prefix for `get_dptf_platform_info()`Subrata Banik
This patch makes the SoC specific callback code more readable by adding `soc_` prefix into the `get_dptf_platform_info()`. In nutshell this patch renames `get_dptf_platform_info()` to `soc_get_dptf_platform_info()`. TEST=Able to build Google/Rex without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27d6a146d5928e1742f82f85f51ad42656f46344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-12-21soc/intel/{adl,mtl,tgl}: Drop unnecessary `dptf.asl`Subrata Banik
This patch drops unused `dptf.asl` from the latest IA SoC platforms as DPTF ACPI code generation is now relies on runtime aka SSDT rather than having fixed dptf.asl files to include inside the mainboard dsdt.asl. TEST=Able to build Google/Kano without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I30a53eace89bf5324d7c2f15c6c2d2218f90eaf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71087 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-20src/soc: Remove unneeded <assert.h>Elyes Haouas
As _Static_assert() is a compiler built-in, <assert.h> is not needed. Change-Id: I578b4bf286538d0606569d19ec760a1846c8145b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-15treewide: Remove unused 'include <arch/io.h>'Elyes Haouas
Change-Id: I6f1d7625eb457084ba893b25518fdfdb59cf64db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-10soc/intel: Move TCSS FW latency macros to IA common tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from SoC specific tcss.h to IA common tcss.h Additionally, ensure other structure definitions belonging to the IA common code tcss.h are not causing compilation issues for ASL files (due to including FW latency macros) hence, guarded against `!defined(__ACPI__)`. TEST=Able to build and boot Google/Rex and Google/Kano. Change-Id: Id51545ef714979c6ba09a2b468231b1f4bab0be7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70487 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/tigerlake: Move TCSS FW latency macros to tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from `tcss_pcierp.asl` to SoC specific `tcss.h`. TEST=Able to build and boot Google/Volteer. Change-Id: I96416f3b68d853c9a5a44c499719f154aa15f0ca Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70486 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07soc/intel: Set IO APIC DMAR entry based on hwArthur Heymans
This avoids the need to hardcode the IOAPIC ID. Change-Id: I0965b511e71c58f1c31433bc54595a5fabb1c206 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70268 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-05soc/intel/tigerlake: Fix setting `HyperThreading`Angel Pons
The `HyperThreading` FSP UPD is set according to the `hyper_threading` CMOS option using the value of the `FSP_HYPERTHREADING` Kconfig option as fallback in case options are disabled or otherwise unavailable. The `HyperThreadingDisable` devicetree setting isn't used by any mainboard but it overwrites the value of the FSP UPD. Remove it so that the CMOS and Kconfig options work as intended. Change-Id: Iea60b89f6f970eb9aee8c7bec026ab5c2df30205 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69534 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/cmn/cse: Create another config for sending CSE EOP cmd lateSubrata Banik
Presently, coreboot supports two instances of sending EOP cmd to the Intel CSE. 1. Sending EOP cmd to CSE during `.final` operation from cse pci driver. 2. Starting with Alder Lake, the recommendation was to send EOP to CSE earlier than CSE `.final` operation. Since then it's referred to as `Sending EOP Early`. This method helped to save the CSE EOP response time significantly. During Meteor Lake platform, CSE EOP response time has become non-deterministic and we have figured that sending EOP command later than CSE .final operation is actually helping to optimize the boot time significantly (around ~150ms savings compared to sending from `.final` ops and ~5sec compared to sending CSE early). Hence, this patch intended to create yet another kconfig for sending CSE late (specifically after `.final` operation). The idea for this newer config is to use the boot state machine for sending CSE EOP cmd. The patch train in this series would add the specific changes to allow sending EOP late and perform other essential operations required prior booting to OS as coreboot decided to skip calling into FSP Notify phase. Starting with Jasper Lake, coreboot sends EOP before loading payload hence, this config is applicable for those platforms. The current plan is that Intel Jasper Lake, Tiger Lake and Meteor Lake platform will select this newer config from SoC code. BUG=b:260041679 TEST=Able to send EOP command successfully for Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69976 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-28sb,soc/intel: Address TCO SECOND_TO_STS name collisionKyösti Mälkki
Later soc/intel/common/smbus addresses TCO2_STS as a separate 16-bit register, while baytrail and braswell assumes 32-bit wide TCO1_STS to extend as TCO2_STS. In src/soc/intel/denverton_ns: #define TCO2_STS_SECOND_TO 0x02 In soc/intel/baytrail,braswell: #define SECOND_TO_STS (1 << 17) Elsewehere #define SECOND_TO_STS (1 << 1) It's expected that we remove the first (1 << 17) case and only access TCO2_STS as a separate 16-bit register. For now, use unique names to avoid confusion. Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26src/soc/intel: Remove unnecessary space after castsElyes Haouas
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-17soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fillDavid Milosevic
The dimm_info structure (defined in src/include/memory_info.h) currently does not hold information about the DIMM's node/controller ID. This patch extends the dimm_info structure by adding a new field for the node ID, called node_num. Also, adapt the dimm_info_fill() function accordingly to populate the newly-added field. Background: These changes are necessary for the Atlas mainboard, where we are currently experiencing issues with the DIMMs device/bank locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a distinct NODE ID. By looking at the smbios table we see Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order to distinguish them. This patch was tested by building and booting for the Alderlake-P RVP board, which has the same DIMM slot configuration as the Prodrive Atlas mainboard. Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68525 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-08soc/intel: Use `PWRMBASE` over static `Index 0` for PMCSubrata Banik
This patch replaces static index 0 for PMC read resources with PCI configuration offset 0x10 (PWRMBASE). TEST=Able to build and boot Google, Rex to OS. Without this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 With this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iee2523876a8045e70effd5824afc327d1113038b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-04soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: I7da9c672ee230dfaebd943247639b78d675957e4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-31soc: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-25soc/intel/tigerlake: Clean up includesElyes Haouas
Change-Id: I9c75e900d05d16de830c750f074df84bb17f64dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-10-22payloads/edk2: Disable the CPU Timer Lib unless supportedSean Rhodes
For recent X86 CPUs, the 0x15 CPUID instruction will return Time Stamp Counter Frequence. For CPUs that do not support this instruction, EDK2 must include a different library which is the reason why this must be configured at build time. If this is enabled, and the CPU doesn't support 0x15, it will fail to boot. If is not enabled, and the CPU does support 0x15, it will still boot but without support for the leaf. Consequently, disabled it by default. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-12soc/intel: Kconfig: Correct UART source clock value in commentWonkyu Kim
Correct UART source clock value in comment from 120 MHz to 100 MHz. BUG=b:249530903 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ifc17357051ae0b3bc663da467b4fc809a46024d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68286 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7ddb4ea792b9a2153b7c77d2978d9e1c4544535d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-27acpi/acpi_pm.c: refactor acpi_pm_state_for_* functionsFabio Aiuto
Use just one function to get the chipset powerstate and add an argument to specify the powerstate claimer {RTC,ELOG,WAKE} and adjust the failure log accordingly. TEST: compile tested and qemu emulation successfully run Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I8addc0b05f9e360afc52091c4bb731341d7213cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/67618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-22soc/intel/spi: Move BIOS flash SPI controllers to fast SPI driverWerner Zeh
There are two classes of SPI controllers on Intel chipsets: * generic usable SPI controllers * SPI controller hosting the BIOS flash (fast SPI controller) While the first class can be used for generic peripheral attachment the second class mostly controls the BIOS flash and a TPM device (if enabled). The generic SPI driver is not fully applicable to the fast SPI controller. In addition, the fast SPI controller reports the reserved MMIO range used for the BIOS flash mapping so that the OS is aware of this range. This patch moves the fast SPI controller of all known SoCs to the fast SPI driver in common code. In addition, the PCI device for the fast SPI controller is removed from the function 'spi_soc_devfn_to_bus' as this is a callback of the generic SPI driver. Change-Id: Ia881c1d274acdcf7f042dd8284048a7dd018a84b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-21soc/intel: Enable TME based on supported CPU SKU and config optionSubrata Banik
This patch removes the static kconfig being used to fill in TME enable FSP UPD. Instead use`is_tme_supported()` and `CONFIG(INTEL_TME)` to check if the CPU has required TME support rather than hardcoding. TEST=FSP debug log shows `TmeEnable` UPD is set appropriately for the TME-supported CPU SKUs. As per FSP-M debug log: Without this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x1 With this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8aa2922baaf2a49e6e2762d31eaffa7bdcd43b0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66750 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21soc/intel: Unravel `INTEL_TME` Kconfig optionAngel Pons
The `INTEL_TME` Kconfig option has a prompt, which means it is meant to be user-configurable. However, it has been selected from Alder Lake and Meteor Lake Kconfig, so `INTEL_TME` cannot be disabled on them. Replace the `select INTEL_TME` statements with default values in order for this option to be user-configurable on all platforms that support it. Change-Id: Ib37c108fcc1004840b82be18fd23c340a68ca748 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66756 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-18soc/intel/tigerlake/fsp_params.c: Add INT D routing for PEG60Frans Hendriks
Debian 11 reports ´0:6:0 can´t derive routing for PCI INT D´. Use FIXED_INT_PIRQ for INT D to PIRQ routing table. BUG=NA TEST=Boot Debian 11 on Siemens AS_TGL1 and verify no PIRQ error message in ´dmesg´ Change-Id: If38c7b6f664e0f6533e583ce62504281a4092720 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-17soc/intel/tigerlake: Disable DISPLAY_FSP_VERSION_INFO on IOTFrans Hendriks
Build error for platforms using Intel FSP for TGL_IOT (FSP_TYPE_IOT). File FirmwareVersionInfoHob.h does not exist in Intel FSP TGL IOT package. File FirmwareVersionInfoHob.h is included when DISPLAY_FSP_VERSION_INFO is enabled. Enable this config for non TGL_IOT only. BUG = NA TEST = Verify that DISPLAY_FSP_VERSION_INFO is disabled by default for TGL_IOT configuration (Build Siemens AS_TGL1). Change-Id: Ief5a7222daf6f1658e8dc04f97b4ddc2bcb74905 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66636 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-10soc/intel/tigerlake: Add USBOTG and CrashLog to irq tableFrans Hendriks
FSP reports missing IRQ for devices. Add USBOTG (D20:F1) and CrashLog & Telemetry (D10:F0) to irq_constrain. Bug = N/A TEST = Build and boot Siemens AS-TGL1 Change-Id: Ic02d33045a07a6888ba97d8f2c6fa71bc7e363e8 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-07soc/intel/tigerlake: Expose In-Band ECC config to mainboardFrans Hendriks
Support for feature "In-Band ECC" not available for Tiger Lake Similar to Elkhart Lake, Tiger Lake also provides this feature. Ported from Elkhart Lake (CB:55668) Bug = N/A TEST = Build and boot Siemens AS-TGL1 Change-Id: Ie54d5f6a9747fad0105d0f8bf725be611bb8cf60 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-20soc/intel/common/pch: Decouple CLIENT from BASEAngel Pons
In preparation to add a third option, have "Client" platforms select a dedicated Kconfig option instead of the common "_BASE" option. Rewrite the help texts to clarify what "Client" and "Server" mean, because the terms refer to the type of silicon and not to the market segment. Some uniprocessor (single-socket) servers are actually client platforms and there are some multi-socket workstations based on a server platform. Change-Id: I646729d709f60ca2b5e74df18c2b4e52f9b10e6b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-27soc/intel/*/Kconfig: Fix typo in commentAngel Pons
clcok ---> clock Change-Id: Ie41524f6500479162984fa9050d942f4e295f00a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-22soc/intel/tigerlake: Replace spaces with tabsSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9b64375d905d93a8db726202ed2ce932fa536da3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-04soc/intel: Rename heci_init to cse_initSubrata Banik
This patch renames heci_init() to cse_init() as HECI initialization should have a bigger scope than just initializing the CSE (a.k.a HECI1 alone). BUG=none TEST=Able to build and boot google/taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-02soc/intel/common/cpu: Use SoC overrides to set CPU privilege levelSubrata Banik
This patch implements a SoC overrides to set CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-05-28soc/intel/tgl: Add PEG devices to PCI constraintsTim Crawford
Based on the constraints for CML. Fixes the following warnings in Linux on system76/oryp8 and system76/gaze16, which have an NVIDIA GPU on the bridge. pcieport 0000:00:01.0: can't derive routing for PCI INT A pcieport 0000:00:01.0: can't derive routing for PCI INT B This, in turn, resolves an IRQ conflict with the PCH HDA device that would cause a stack trace on every boot and on S3 suspend. irq 10: nobody cared (try booting with the "irqpoll" option) <snip> [<00000000fb84c354>] azx_interrupt [snd_hda_codec] Disabling IRQ #10 Change-Id: Ibc968aaa7bf0259879097ff69d2543dcfa2e5e4b Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-26soc/intel/tigerlake: Hook up FSP hyper-threading setting to option APIFelix Singer
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the mainboard starlabs/laptop/tgl, since it is obsolete now. Change-Id: I49bbd4a776b4e6c55cb373bbf88a3ca076342e3e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-05-25soc/intel/tigerlake: Drop unused `PCH_DEV_SLOT_LPC` macroSubrata Banik
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the Tiger Lake SoC PCI device list. BUG=none TEST=Able to build and boot volteer, google board. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27a2f31aa706c4d76e9f0db202422bc129368959 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-05-16soc/intel/*: Fix up header guardsArthur Heymans
Change-Id: If9ae375629c8af3d32b4c5493b5d63203e8847aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-16soc/intel/*: Use SSDT to pass A4GB and A4GSArthur Heymans
GNVS is more fragile as you need to keep struct elements in sync with ASL code. Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16soc/inte/*/gpio; Add GPE_EN and GPE_STS register definitionMaulik V Vaghela
coreboot needs to set GPE_EN bit for the GPIOs which are wake capable from s0ix/sleep. Due to GPIO locking mechanism, coreboot/OS will not be able to write GPE_EN register post GPIO has been locked. This patch adds support in SoC code to provide correct offset for GPE_EN and GPE_STS registers to the common code. Plan is to use this offsets to set GPE_EN bits before GPIO locking in coreboot which will be part of subsequent CL. BUG=b:222375516 BRANCH=firmware-brya-14505.B TEST=Check if code compiles for Brya and correct offset values are printed. Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-13soc/intel/tigerlake/meminit.c: Fix clang static assertsArthur Heymans
Clang does not like static asserts on integral constant expressions. Change-Id: If5890a357ed95153d8ae2efa727c111b05bc6455 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-05soc/intel/tigerlake: Add enum for `DdiPortXConfig`Angel Pons
Add an enum for `DdiPortXConfig` devicetree options. Note that setting these options to zero does not disable the corresponding DDI port, but instead indicates that no LFP (Local Flat Panel, i.e. internal LCD) is connected to it. Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2022-04-29soc/{amd/stoneyridge,intel}: Don't select VBOOT_SEPARATE_VERSTAGEArthur Heymans
Now the bootblock is not limited to 64K so integrating vboot into the bootblock reduces the binary size. intel/apl is an exception since the bootblock size is limited to 32K. Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-29soc/intel: Decouple HECI disabling interface from HECI disable KconfigSubrata Banik
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG recommends to disable the CSE PCI device while CSE is in software temporary disable state. BUG=b:228789015 TEST=Able to build google/redrix. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I66abc04d5e195515165a77b0166d004f17d029e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-27soc/intel/cmn/lockdown: Perform SA lockdown configurationSubrata Banik
`sa_lockdown_cfg` function ensures locking the PAM register hence, skip dedicated calling into `sa_lock_pam()` from the SoC `finalize.c` file. Dropped sa_lock_pam() call from ADL/CNL/EHL/JSL and TGL. Additionally, this patch enforces SA lockdown configuration for SKL and ICL as well. BUG=b:211954778 TEST=Able to build google/brya with these changes. > localhost ~ # lspci -xxx | less 00:00.0 Host bridge: Device 8086:4601 (rev 04) Bit 0 for all PAM registers a.k.a, PAMx_0_0_0_PCI.LOCK bit is set (meaning locked). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-22soc/intel: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: I529c822c9e952dae6613d3de64f6709e0fd9b385 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-20soc/intel: clean up dmi driver codeWonkyu Kim
1. Remove dmi.h as it's migrated as gpmr.header 2. Remove unused gpmr definitions 3. For old platforms, define DMI defintions in c code for less code changes. TEST=Build Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-06soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODESridhar Siricilla
The patch SOC_INTEL_COMMON_BASECODE Kconfig for Comet Lake, Jasper Lake and Tiger Lake SoCs. It allows access to intelbasecode/debug_feature.h for Comet Lake, Jasper Lake and Tiger Lake SoCs. TEST=Build code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06soc/intel/common: Abstract the common TCSS functionsJohn
This change abstracts the common TCSS functions for pad configuration and Thunderbolt authentication. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-29soc/intel: Move `pmc_clear_pmcon_sts()` into IA common codeSubrata Banik
This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances. Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. Typically, there are two possible ways to perform GEN_PMCON_A register programming (like `pmc_clear_pmcon_sts()`) as: 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to perform GEN_PMCON_A register programming using PMC MMIO. BUG=b:211954778 TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeff Daly <jeffd@silicom-usa.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-03-15soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC KconfigMichael Niewöhner
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to 512 in the SoC Kconfig and drop it from the mainboard Kconfigs. Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-15{mb, soc}: Move mrc_cache invalidating logic into `memory` common codeSubrata Banik
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15soc/intel/common: Pass `FSPM_UPD *` argument for spd functionsSubrata Banik
This patch adds `FSPM_UPD *` as argument for mem_populate_channel_data() and read_spd_dimm(). This change will help to update the architectural FSP-M UPDs in read_spd_dimm(). BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I770cfd05194c33e11f98f95c5b93157b0ead70c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-08soc/intel/tgl: chipset devicetree: correct TraceHub device aliasMichael Niewöhner
Device 1f.7 is TraceHub, not the PCH Thermal device, which doesn't exist anymore on TGL. Correct the device´s alias. Reference: Intel doc# 631119-007 Change-Id: I30a4ab1e801f6cdb0f2e03f105bf8cc09592eed8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-08soc/intel/tgl: drop orphaned VR domains enumMichael Niewöhner
Change-Id: I937bdf032e1ed86900334d41655f3e6272f66a6f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-07soc/intel/tigerlake: Hide PMC and IOM devicesMichał Kopeć
Windows complains on missing drivers for these ACPI devices. Hide them from OS as it doesn't influence the hardware operation. Linux can still probe the drivers correctly. TEST=Boot Windows 11 and see there are no devices with missing drivers. Boot Ubuntu 20.04 and check that drivers corresponding to ACPI HIDs are still probed. Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: I6c30c08ab730749bddef7ea67c7470c1554bd572 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-02mb, soc: Add the SPD_CACHE_ENABLEZhuohao Lee
In order to cache the spd data which reads from the memory module, we add SPD_CACHE_ENABLE option to enable the cache for the spd data. If this option is enabled, the RW_SPD_CACHE region needs to be added to the flash layout for caching the data. Since the user may remove the memory module after the bios caching the data, we need to add the invalidate flag to invalidate the mrc cache. Otherwise, the bios will use the mrc cache and can make the device malfunction. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and enable this feature to the brask the device could speed up around 150ms with this feature. Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25intelblocks/pcie: Correct mapping between LCAP port and coreboot indexMAULIK V VAGHELA
coreboot uses port index which is 0 based for all PCIe root ports. In case of PCIe remapping logic, coreboot reads LCAP register from PCIe configuration space which contains port number (mostly 1 based). This assumption might not be true for all the ports in coreboot. TBT's LCAP registers are returning port index which are based on 2. coreboot's PCIe remapping logic returns port index based on index 1. This patch adds variable to pcie_rp_config to pass lcap_port_base to the pcie remapping function, so coreboot can map any n-based LCAP encoding to 0-based indexing scheme. This patch updates correct lcap_port_base variable for all PCIe root ports for all SOCs, so that function returns correct 0-based index from LCAP port number. BUG=b:210933428 BRANCH=None TEST=Check if code compiles for all ADL boards Change-Id: I7f9c3c8e753b982e2ede1a41bf87d6355b82da0f Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61936 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25arch/x86: factor out and commonize HPET_BASE_ADDRESS definitionFelix Held
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000, so define this once in arch/x86 and include this wherever needed. The old AMD AGESA code in vendorcode that has its own definition is left unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-02-18drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik
This patch renames all FSP Notify Phase API configs to primarily remove "SKIP_" prefix. 1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM -> USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT -> USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE -> USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE The idea here is to let SoC selects all required FSP configs to execute FSP Notify Phase APIs unless SoC deselects those configs to run native coreboot implementation as part of the `.final` ops. For now all SoC that uses FSP APIs have selected all required configs to let FSP to execute Notify Phase APIs. Note: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. Additionally, fixed SoC configs inclusion order alphabetically.  BUG=b:211954778 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15soc/intel/*/pmc: Add `finalize` operation for pmcSubrata Banik
This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs, i.e., Ready to Boot and End Of Firmware. Additionally, move the PMCON status bit clear operation to `.final` ops to cover any such chances where FSP-S Notify Phase or any other later boot stage may request a global reset and PMCON status bit remains set. BUG=b:211954778 TEST=Able to build brya with these changes. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a0b869849d5d8c76031b8999f3d28817ac69247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-05cpu/x86/lapic: Move LAPIC configuration to MP initKyösti Mälkki
Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init(). In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs. Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-02soc/intel/tigerlake: Use PMC IPC to disable HECI1Subrata Banik
This patch allows common CSE block to disable HECI1 device using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for Tiger Lake to disable HECI1 device using PMC IPC. Additionally, remove dead code that deals with HECI1 disabling using in SMM as HECI1 disabling using PMC IPC is simpler solution. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02soc/intel/common/cse: Rework heci_disable functionSubrata Banik
This patch provides the possible options for SoC users to choose the applicable interface to make HECI1 function disable at pre-boot. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for disabling heci1 using non-posted sideband write (inside SMM) after FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for disabling heci1 using private configuration register (PCR) write. Applicable for SoC platform prior to CNL PCH. Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the compilation failure. Finally, rename heci_disable() function to heci1_disable() to make it more meaningful. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-28soc/intel: Abstract the common block API for TCSS registers accessJohn Zhao
The existing TCSS registers access is through the REGBAR. There will be future platforms which access the TCSS registers through the Sideband interface. This change abstracts the common block API for TCSS access. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I3e2696b117af24412d73b257f470efc40caa5022 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-19soc/intel/common/cpu: Use SoC overrides to get CPU privilege levelSubrata Banik
This patch implements a SoC overrides to check CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 12:53:56 +0000