coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-02-02	soc/intel/tigerlake: Use PMC IPC to disable HECI1	Subrata Banik
2022-02-02	soc/intel/common/cse: Rework heci_disable function	Subrata Banik
2022-01-14	soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` config	Subrata Banik
2021-05-07	soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster	Kane Chen
2021-02-15	soc/intel: Remove unused <console/console.h>	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-12	soc/intel/*/smihandler: Only compile in TCO SMI handler if needed	Patrick Georgi
2020-02-25	soc/intel/common/block: Move cse common functions into block/cse	Subrata Banik
2020-02-25	soc/intel/common/block: Move smihandler common functions into common code	Subrata Banik
2019-11-09	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik