coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-02-22	soc/intel/tigerlake: Add CrashLog implementation for intel TGL	Francois Toguo
2021-01-25	soc/intel/tigerlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGD	Bora Guvendik
2020-09-30	soc/intel/tigerlake: Set TME upd param based on config	Pratik Prajapati
2020-09-21	soc/intel: rename get_prmrr_size	Michael Niewöhner
2020-09-08	soc/intel/tigerlake: Skip GPIO configuration from FSP	Srinidhi N Kaushik
2020-08-24	soc/intel/tigerlake: Fix IPU and Vtd config	Ravi Sarawadi
2020-07-28	soc/intel/tigerlake: Simplify is-device-enabled checks	Felix Singer
2020-07-26	soc/intel/tigerlake: Disable CPU PCIe in FSP	Shaunak Saha
2020-07-26	soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform	John Zhao
2020-07-09	mainboard/intel/tglrvp: Remove unused PrmrrSize chip config	Subrata Banik
2020-06-30	soc/intel/tigerlake: Add CpuReplacementCheck to chip options	Jamie Ryu
2020-06-22	soc/intel/tigerlake: Add CmdMirror option in chip.h	David Wu
2020-05-30	soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En	John Zhao
2020-05-18	soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En	John Zhao
2020-05-18	soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect override	Eric Lai
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-04	src/soc/tigerlake: Update SerialIoDebugMode UPD in FSP-M	Srinidhi N Kaushik
2020-05-01	soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understa...	Subrata Banik
2020-04-20	soc/intel/tigerlake: Update iDisp Link UPD settings	Srinidhi N Kaushik
2020-04-20	soc/intel/tigerlake: Merge the recent change from other platforms	Wonkyu Kim
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-04-01	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra
2020-01-13	soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig	Maulik V Vaghela
2019-11-09	soc/intel/tigerlake/romstage: Do initial SoC commit till romstage	Subrata Banik