coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-09-23	soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registers	Michael Niewöhner
2021-05-06	soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities	Tim Wawrzynczak
2021-05-06	soc/intel/tigerlake: Add known GPIO virtual wire information	Tim Wawrzynczak
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-05-06	soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel	Shaunak Saha
2020-04-01	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra
2020-03-03	soc/intel/tigerlake: Add Jasper lake GPIO support	Ronak Kanabar
2020-01-25	soc/intel/tigerlake: Fix GPIO communities	Shaunak Saha
2020-01-22	soc/intel/tigerlake: Update GPIO config	Ravi Sarawadi
2019-11-09	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik