coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-08-26	soc/intel/tigerlake: Lock PAM registers in finalize	Tim Wawrzynczak
2021-08-04	Move post_codes.h to commonlib/console/	Ricardo Quesada
2020-10-26	src: Include <arch/io.h> when appropriate	Elyes HAOUAS
2020-10-19	soc/intel/*: drop useless XTAL shutdown qualification code	Michael Niewöhner
2020-10-03	soc/intel: Make use of PMC low power program from common block	Subrata Banik
2020-07-07	soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus master	John Zhao
2020-07-06	soc/intel: Drop unused `#include <reg_script.h>`	Angel Pons
2020-06-16	arch/x86: Create helper for APM_CNT SMI triggers	Kyösti Mälkki
2020-05-26	soc/intel/tigerlake: Remove MIPI clock setting from devicetree	Srinidhi N Kaushik
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-01-16	soc/intel/{cnl,icl,skl, tgl}: Move SOC_INTEL_COMMON_BLOCK_THERMAL into SoC sp...	Subrata Banik
2019-12-19	src/soc/intel: Remove unused <stdlib.h>	Elyes HAOUAS
2019-11-09	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik