coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-12-10	soc/intel/tigerlake: Check TBT & TCSS ports for wake events	Tim Wawrzynczak
2020-12-10	soc/intel/common: Adapt XHCI elog driver for reuse	Tim Wawrzynczak
2020-11-10	soc/intel/tigerlake: Log PM event from an internal device	Karthikeyan Ramasubramanian
2020-11-09	soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log	Tim Wawrzynczak
2020-08-18	elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE	Aaron Durbin
2020-07-26	src: Remove unused 'include <cbmem.h>'	Elyes HAOUAS
2020-06-03	soc/intel/tigerlake: update elog to include CSME reset causes	derek.huang
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-11-09	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik