| Age | Commit message (Expand) | Author |
|---|
| 2024-03-05 | soc/intel: Add definition of D0 stepping for TigerLake Halo | Alicja Michalska |
| 2022-11-26 | src/soc/intel: Remove unnecessary space after casts | Elyes Haouas |
| 2022-11-04 | soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h> | Elyes Haouas |
| 2022-10-25 | soc/intel/tigerlake: Clean up includes | Elyes Haouas |
| 2022-04-20 | soc/intel: clean up dmi driver code | Wonkyu Kim |
| 2022-03-07 | src: Make PCI ID define names shorter | Felix Singer |
| 2021-10-01 | soc/tigerlake: Make IO decode / enable register configurable | Sean Rhodes |
| 2021-08-24 | soc/intel/tgl: Add PCR_PSF3_T0_SHDW_PMC_REG_BASE for PCH-H | Jeremy Soller |
| 2021-08-24 | soc/intel: Add TGL-H CPUID | Jeremy Soller |
| 2021-08-19 | soc/intel/common: Add TGL-H PCI IDs | Jeremy Soller |
| 2021-08-04 | Move post_codes.h to commonlib/console/ | Ricardo Quesada |
| 2021-07-17 | soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h' | Subrata Banik |
| 2021-03-01 | soc/intel: Drop `bootblock_cpu_init()` function | Angel Pons |
| 2021-01-31 | soc/intel/*: drop incomplete and unneeded check for DMI SRLOCK | Michael Niewöhner |
| 2021-01-25 | soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroring | Michael Niewöhner |
| 2020-12-09 | soc/intel/common/dmi: Move DMI defines into DMI driver header | Srinidhi N Kaushik |
| 2020-11-29 | soc/intel: Configure P2SB before other PCH controllers | Furquan Shaikh |
| 2020-08-26 | soc/intel/tigerlake: Rename pch_init() code | Alexey Buyanov |
| 2020-08-07 | soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE | Subrata Banik |
| 2020-08-05 | {nb,soc}/intel: Use get_current_microcode_rev() for ucode version | Subrata Banik |
| 2020-07-25 | soc/intel/tigerlake: Update Tiger Lake SA IDs | Derek Huang |
| 2020-07-12 | soc/intel/tigerlake: Move tco_configure to bootblock | Tim Wawrzynczak |
| 2020-07-12 | soc/intel/tigerlake: Add new IGD device | Ravi Sarawadi |
| 2020-07-04 | soc/intel/tigerlake: Remove unused EHL DID from TGL SoC | Subrata Banik |
| 2020-06-06 | soc/intel/tigerlake: Add CPU ID for TGL B0 | Jamie Ryu |
| 2020-06-03 | soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register | Elyes HAOUAS |
| 2020-06-02 | {icelake,jasperlake,skylake,tigerlake}/bootblock.c: Clean up includes | Elyes HAOUAS |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-04-06 | soc/intel/tigerlake: Use SPDX for GPL-2.0-only files | Angel Pons |
| 2020-04-01 | soc/intel/tigerlake: Remove Jasper Lake SoC references | Aamir Bohra |
| 2020-03-18 | soc: Remove copyright notices | Patrick Georgi |
| 2020-02-25 | soc/intel/common: Update Jasper Lake Device IDs | Meera Ravindranath |
| 2020-02-17 | soc/tigerlake: Add Device id for Tiger Lake Dual Core | Srinidhi N Kaushik |
| 2020-02-17 | soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 | Wim Vervoorn |
| 2020-02-17 | soc/intel{cnl,icl,skl,tgl}/bootblock: Make sure DMI PCR 2770 is set | Wim Vervoorn |
| 2020-02-15 | soc/intel/tigerlake: Update PMC Register Base and platform check for JSP | Usha P |
| 2020-01-22 | soc/intel/common: Add Elkhartlake Device IDs | Tan, Lean Sheng |
| 2020-01-08 | soc/intel/tigerlake: Fix PMC config | Ravi Sarawadi |
| 2019-12-19 | soc/intel/tigerlake: Add required header files in pch.c | Aamir Bohra |
| 2019-12-16 | soc/intel/tigerlake: Pick correct pmc base reg from pch type | Maulik V Vaghela |
| 2019-12-10 | soc/intel/common: Add Jasperlake Device IDs | rkanabar |
| 2019-11-15 | soc/intel/{icl,tgl}: Rename pch_early_init() to pch_init() | Subrata Banik |
| 2019-11-14 | soc/intel/tigerlake: Include few more Tigerlake device IDs | Subrata Banik |
| 2019-11-09 | soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock | Subrata Banik |
