coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-03-15	soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI device	Cliff Huang
2020-05-12	soc/intel/tigerlake: Correct IRQ interrupt	Wonkyu Kim
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-05-04	soc/intel/tigerlake: Update interrupt setting	Wonkyu Kim
2020-04-07	soc/intel/tigerlake/acpi: Fix typo in HDA in comment	Subrata Banik
2020-04-01	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-02-19	soc/tigerlake: Add IRQ header and ACPI support for JSP	Meera Ravindranath
2020-01-22	soc/intel/tigerlake: Update interrupt info	Wonkyu Kim
2019-11-09	soc/intel/tigerlake/acpi: Copy acpi directory from icelake	Subrata Banik