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2021-08-13soc/intel/tgl: Hook up ucode for TGL-U and TGL-RTim Crawford
Hook up microcode from 3rdparty repo for: - TGL-U: 06-8c-01 (CPUID signature: 0x806c1) - TGL-R: 06-8c-02 (CPUID signature: 0x806c2) Verified microcode blob was found in CBFS on system76/darp7 (TGL-U). CBFS: Found 'cpu_microcode_blob.bin' @0x103c0 size 0x31c00 in mcache @0x76c2d0ac microcode: sig=0x806c1 pf=0x80 revision=0x88 coreboot reports the correct revision for the microcode. Change-Id: I210c0133dad7ade63b9f7177aaa9a69b019469af Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56862 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans
This removes the need to include this code separately on each platform. Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-06soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias padsTim Wawrzynczak
TGL boards using the Type-C subsystem for USB Type-C ports without a retimer attached may require a DC bias on the aux lines for certain modes to work. This patch adds native coreboot support for programming the IOM to handle this DC bias via a simple devicetree setting. Previously a UPD was required to tell the FSP which GPIOs were used for the pullup and pulldown biases, but the API for this UPD was effectively undocumented. BUG=b:174116646 TEST=Verified on volteer2 that a Type-C flash drive is enumerated succesfully on all ports. Verified all major power flows (boot, reboot, powerdown and S0ix/suspend) still work as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-13dptf: Move platform-specific information to `struct dptf_platform_info`Tim Wawrzynczak
DPTF HIDs are different per-platform going forward, so refactor these into SoC-specific structures which the DPTF driver can query at runtime for platform-specific information. Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-28soc/intel/tigerlake: Move TCSS code to intel/common/blockTim Wawrzynczak
The Type-C subsystem ("TCSS") IP block is similar between TGL and ADL. For pre-boot purposes, the limited amount of functionality required appears to be common between the two, therefore move the functionality to intel/common/block and rename from `early_tcss to `tcss` along the way. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1c6bb9c7098691f0c828f9d5ab4bd522515ae966 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51753 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during bootBrandon Breitenstein
TCSS muxes being left uninitialized during boot is causing some USB3 devices to downgrade to USB2 speed. To properly configure the Type C ports the muxes should be set to disconnected state during boot so that the port mapping of USB2/3 devices is properly setup prior to Kernel initializing devices. BUG=b:180426950 BRANCH=firmware-volteer-13672.B TEST= Connected USB3 storage device and rebooted the system multiple times to verify that devices were no longer downgrading to USB2 speed. Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03soc/intel: Factor out common smmrelocate.cAngel Pons
There are seven identical copies of the same file. One is enough. Change-Id: I68c023029ec45ecfaab0e756fce774674bb02871 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50937 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Drop `bootblock_cpu_init()` functionAngel Pons
Just call `fast_spi_cache_bios_region()` directly instead. Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50952 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22soc/intel/tigerlake: Add CrashLog implementation for intel TGLFrancois Toguo
CrashLog is a diagnostic feature for Intel TGL based platforms. It is meant to capture the state of the platform before a crash. The state of relevant registers is preserved across a warm reset. BUG=None TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-13soc/intel/tigerlake: Add code for early tcssBrandon Breitenstein
In order for USB Type-C idisplays to be detected prior to loading Kernel PMC IPC driver is needed to communicate with PMC in order to correctly set the USB Mux settings. This patch is adding in support for early detection of both Displays. BUG=b:151731851 BRANCH=NONE TEST=built and verified that TCSS MUX is being set on Volteer Change-Id: I58e66f21210d565fb8145d140d2fc7febecdd21a Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42079 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-10soc/intel/tigerlake: Log PM event from an internal deviceKarthikeyan Ramasubramanian
Add support to check for the Power Management (PM) Status bit for various internal devices like USB, CNVi etc. and log them into the event log for debugging purposes. BUG=b:172279037 BRANCH=volteer Change-Id: Ib3d0bf33d780444f8240f749a3319212c985950d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-03soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ixFurquan Shaikh
This change adds elog.c to smm-y for Tiger lake and Jasper Lake platforms to enable the logging of wake sources in eventlog for S0ix. BUG=b:172272078,b:169731044 BRANCH=volteer TEST=Verified on volteer that wake sources are correctly logged for S0ix: 8 | 2020-11-02 13:54:27 | S0ix Enter 9 | 2020-11-02 13:54:33 | S0ix Exit 10 | 2020-11-02 13:54:33 | Wake Source | RTC Alarm | 0 11 | 2020-11-02 13:54:49 | S0ix Enter 12 | 2020-11-02 13:54:54 | S0ix Exit 13 | 2020-11-02 13:54:54 | Wake Source | Power Button | 0 14 | 2020-11-02 13:55:04 | S0ix Enter 15 | 2020-11-02 13:55:10 | S0ix Exit 16 | 2020-11-02 13:55:10 | Wake Source | GPE # | 112 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ie1c40dfba6c82ca45a21d35c5a2725e4d30855d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47141 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/intel/gma: Implement fsp_soc_get_igd_bar() in common codeNico Huber
`fsp/util.h` draws incompatible UDK headers in. Hence, we have to declare it locally again. Change-Id: Iaa5981088eeb5c36f765d6332ae47a38a6a4c875 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40729 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-22soc/intel/tigerlake: Provide SoundWire controller propertiesDuncan Laurie
The Intel Tigerlake SoundWire controller has 4 master links which are configured differently depending on the external crystal oscillator which is connected to the PCH. This function will read the PCH PMC EPOC register to determine the frequency and then fill out the master link entries with the correct table values. The frequency is also provided directly in a custom "ip-clock" property which will be added to the link descriptor and passed to the OS driver so it can know the clock rate of the master. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I98b7df21210c29cd8defeff648f2c2207d629295 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-20soc/intel/tigerlake: Move pmc_soc_set_afterg3_en to pmutilTim Wawrzynczak
pmc.c was included in the SMM object, but only needed the one function, pmc_soc_set_afterg3_en. pmutil.c was already doing power management- related functionality, and was included in SMM, so moving pmc_soc_set_afterg3_en to pmutil.c allows pmc.c to be removed from the SMM build. Change-Id: I87f65fd10d35f1f75516e804501d5319b81a0383 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41407 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-17soc/intel/tigerlake: Remove eMMC/SD supportDuncan Laurie
Tigerlake platform does not have built in eMMC/SD support so all this code is unused and can be removed. Change-Id: I70ff983d175375171d5a649378f32f1062c0876d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40372 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14soc/intel/{icl,tgl}: Make use of print_me_fw_version() from CSE libKrishna Prasad Bhat
Make use of print_me_fw_version() which is defined in the CSE lib to print ME firmware version information for icl,tgl. BUG=None BRANCH=None TEST=Build and boot iclrvp, tglrvp boards. Change-Id: Ief75403c490eee499a84372e54fa38ea3016cc11 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-01soc/intel/tigerlake: Remove Jasper Lake SoC referencesAamir Bohra
This implementation removes all JSL references from the TGL SoC code. Additionally, mainboard code changes are done to support build. BUG=b:150217037 TEST=build tglrvp and volteer Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-01soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoCAamir Bohra
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build. BUG=b:150217037 TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board. Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-20soc/intel: Enable GPIO functions in verstageBora Guvendik
Enable GPIO functionality in verstage so platforms can read a PCH GPIO in verstage to determine recovery mode. BUG=b:151102807 TEST=make build successful Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I4e3b9da307dcf59ab251d8a6a5e09c2a3cfc59fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/39501 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03soc/intel/tigerlake: Add Jasper lake GPIO supportRonak Kanabar
Add gpio definition for Jasper Lake gpio controller. Also created a separate file for JSL and TGL gpio keeping common asl file. gpio_soc_defs.h must pass correct information/macro values to asl file for code to work. GPIO controller includes 4 gpio community and 10 groups. Patch adds definition for all gpio within community and groups Updated IRQ mapping for all gpios TEST=Check if jslrvp and tglrvp code is compiling Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-03-03src/soc/tigerlake: Add memory configuration support for Jasper LakeMeera Ravindranath
BUG=none BRANCH=none TEST=Build and verify boot of WaddleDoo. Change-Id: I8de502d3f05d52b9dae34e3b013c6d5b1896fa85 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-02-09soc/intel/tigerlake: add memory configuration supportNick Vaccaro
Move some of the common memory code that was being performed in mainboard into the soc to reduce redundant code going forward. BUG=b:145642089 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel and verify memory size shows 8GB. Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-13soc/intel/tigerlake: Select correct fsp_param as per SoC KconfigMaulik V Vaghela
New Kconfig for Jasperlake soc was created and fsp_param for Jasperlake has differences compared to Tigerlake. Thus renaming fsp_params.c to fsp_params_tgl.c to point out correct file as per soc selected. Also adding new file for fsp_param_jsl for Jasperlake SoC and currently its the copy of fsp_param_tgl. TODO: update files with correct fsp_params Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37267 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02soc/intel/tigerlake: Change compilation based on TIGERLAKE_BASEMaulik V Vaghela
since we support JSL and TGL soc under tigerlake folder, we need to make sure all soc related files get compiled based on CONFIG_SOC_INTEL_TIGERLAKE_BASE and not only for Tigerlake. We can control soc specific file compilation through Kconfig of individual soc. Change-Id: I1a663555d0bdf7588c4e12363375e7c90629f7d9 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-11-09soc/intel/tigerlake: Do initial SoC commit till ramstageSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 5.c Remove dGPU over PCIE enable Kconfig option 6. Add CPU/PCH/SA EDS document number and chapter number 7. Remove unnecessary headers from .c files based on review Tiger Lake specific changes will follow in subsequent patches. 1. Include GPIO controller delta over ICL 2. FSP-S related UPD overrides as applicable Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36087 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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