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Move ADD_VBT_DATA_FILE to "Devices" menu and rename it to
INTEL_GMA_ADD_VBT_DATA_FILE.
Depend on Intel platforms to avoid confusing users of non-Intel platforms.
The Intel GMA driver will use the vbt.bin, if present, to fill the
ACPI OpRegion.
Change-Id: I688bac339c32e9c856642a0f4bd5929beef06409
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Use mca_configure() API from cpulib to configure
Intel Machine Check Architecture (MCA)
Change-Id: Ia96cb82fff3def46dbecb09dee94de86f179abe6
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch uses system agent common library to
know tseg region start and size. Unable to remove smm_region()
function from soc code as SMM common library
is not yet available for skylake use.
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.
Change-Id: If98b65805753db2c30d6fea29e401a17cef39799
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch to avoid build bot hang issue due to no
active default value for UART_FOR_CONSOLE kconfig
option.
Change-Id: I70ca5dc6c4bde6a119ad59d8c58955c96c042198
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21287
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch ensures skylake device using FSP1.1 can use HW based
DRAM top calculation which was broken due to skylake fsp1.1 not
honoring any UPD to know PRMMR size and default reserving 1MB for PRMRR size.
This WA is not needed for FSP2.0 implementation due to
PrmrrSize UPD is available and considering into hw based dram top
calculation.
BRANCH=none
BUG=b:63974384
TEST=Build and boot lars which is using skylake 1.1 fsp.
Change-Id: Iade0d2cb2a290fc4c9f0e6b1eaadc8afff2fa581
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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This patch to ensures that coreboot is performing SPI
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence SPI lock down programming has been moved
right after pci resource allocation is donei, so that
SPI registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure SPIBAR+HSFSTS(0x04) register FLOCKDN bit and WRSDIS
bit is set. Also, Bits 8-12 of SPIBAR+DLOCK(0x0C) register is set.
Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/21064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch to ensures that coreboot is performing DMI
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence BIOS Interface lock down through Sideband
access has been moved right after pci resource allocation is done,
so that BILD lock down is getting executed along with LPC and SPI
BIOS interface lockdown settings before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure DMI register offset 0x274c bit 0 is set.
Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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FSP is doing TCO lock inside Post PCI bus enumeration
NotifyPhase(). Hence remove TCO Lock down programming
from coreboot.
TEST= Ensure TCO_LOCK offset 8 bit 12 is set.
Change-Id: Iec9e3075df01862f8558b303a458126c68202bff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch to ensures that coreboot is performing PMC
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence PMC register lock down has been moved
right after pci resource allocation is done, so that
PMC registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure PMC MMIO register 0xC4 bit 31 is set.
Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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FSP is doing PMC ABASE lock inside Post PCI bus enumeration
NotifyPhase(). Hence remove ABASE Lock down programming
from coreboot.
TEST= Ensure GEN_PMCON_B offset 0xA4 bit 17, 18 is set.
Change-Id: I800e654c7d8dc55cc0e8299501c1f85c57882e9d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch to ensures that coreboot is performing LPC
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence lpc register lock down has been moved
right after pci resource allocation is done, so that
lpc registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure LPC register 0xDC bit 1 and 7 is set.
Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch to provide new config options to perform LPC and SPI
lock down either by FSP or coreboot.
Remove EISS bit programming as well.
TEST=Build and boot Eve and Poppy.
Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch ensures that entire system memory calculation is done
based on host bridge registers.
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve and poppy successfully with below configurations
1. Booting to OS with no UPD change
2. Enable ProbelessTrace UPD and boot to OS.
3. Enable PRMRR with size 1MB and boot to OS.
4. Enable PRMRR with size 32MB and boot to OS.
5. Enable PRMRR with size 2MB and unable to boot to OS due to
unsupported PRMRR size.
Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The Sideband Acces locking code is skipped from FSP by setting an
FSP-S UPD called PchSbAccessUnlock. This locking is being done in
coreboot during finalize.c.
This is done because coreboot was failing to disable HECI1 device
using Sideband interface during finalize.c if FSP already locks
the Sideband access mechanism before that.
So, as a solution, coreboot passes an UPD to skip the locking
in FSP, and in finalize.c, after disabling HECI, it removes the
Sideband access.
BUG=b:63877089
BRANCH=none
TEST=Build and boot poppy to check lspci not showing Intel ME
controller in the PCI device list.
Change-Id: I8dba4c97480200507969b0f2873337f97bd2ff6a
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Configure core PRMRR first on all the cores and then follow
the SGX init sequence. Second microcode load would run the
MCHECK. To pass MCHECK, PRMRR on all cores needs to be
configured first. Hence, PRMRR configuration would be called
from soc_core_init while MP init for each core and then from
soc_init_cpus, BSP would call sgx_configure for each core
(including for itself). This code flow satisfies the MCHECK
passing pre-conditions; and apparently this patch fixes the
behavior of calling configure_sgx() “again” for BSP. (So
removed the TODO comment also).
Change-Id: I88f330eb9757cdc3dbfc7609729c6ceb7d58a0e1
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21007
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove passing microcode patch pointer as param while calling
- soc_core_init()
- soc_init_cpus()
Also change callbacks in apollolake/geminilake and skylake/kabylake
common code to reflect the same function signature.
Change-Id: Ib03bb4a3063d243d97b132e0dc288ef3868a5a7b
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21010
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Get microcode patch pointer from intel_mp_current_microcode() api
of mp_init and change sgx_configure function signature to drop
microcode_patch param.
Change-Id: I9196c30ec7ea52d7184a96b33835def197e2c799
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21009
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select LPSS UART Base address based on LPSS UART port index.
Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Skylake/Kabylake SOC has two possible ways to make serial
console functional.
1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.
This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
PCI based LPSS UART2 is by default enabled for Chrome Design.
Change-Id: I9647820fe59b5d1a1001a611b9ae3580946da0ae
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of enabling power button SMI unconditionally, add a boot state
handler to enable power button SMI just before jumping to
payload. This ensures that:
1. We do not respond to power button SMI until we know that coreboot
is done.
2. On resume, there is no need to enable power button SMI. This avoids
any power button presses during resume path from triggering a
shutdown.
BUG=b:64811381
Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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We do not need or use the Management Engine MBP HOB so that
step can be skipped when FSP initializes the ME.
BUG=b:64479422
TEST=boot with FSP debug enabled binary and ensure that the
output indicates this step is being skipped:
Skipping MBP data due to SkipMbpHob set!
Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/20951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Need to perform a dummy read in order to activate LPSS UART's
16550 8-bit compatibility mode.
TEST=Able to get serial log in both 32 bit and 8 bit mode through
LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and
CONFIG_DRIVERS_UART_8250MEM selection.
Change-Id: I5f23fef4522743efd49167afb04d56032e16e417
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The PCH_P2SB_EPMASK macro takes a parameter. Ensure parenthesis
are put around the parameter expansion.
Change-Id: I978e9397036ea3630434982fe4ecd698877fe0d6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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1. Add a new variable to GNVS to store information during S3 suspend
whether UART debug port controller is enabled.
2. On resume, read stored GNVS variable to decide if UART debug port
controller needs to be initialized.
3. Provide helpers functions required by intel/common UART driver for
enabling controller on S3 resume.
BUG=b:64030366
TEST=Verified behavior with different combinations:
1. Serial console enabled in coreboot: No change in behavior.
2. Serial console enabled only in kernel: coreboot initializes debug
controller on S3 resume.
3. Serial console not enabled in coreboot and kernel: coreboot skips
initialization of debug controller on S3 resume.
Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20886
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Create a new function uart_lpss_init which takes the UART LPSS
controller out of reset and initializes and enables clock.
2. Instead of passing in m/n clock divider values as parameters to
uart_common_init, introduce Kconfig variables so that uart_lpss_init
can use the values directly without having to query the SoC.
BUG=b:64030366
TEST=Verified that UART still works on APL and KBL boards.
Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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In _FSL ACPI notification 0x83 was incorrectly being sent to DPTF.
When there should be no notification on fan speed change.
Change-Id: I66efa7a7feb911a458829a54dbd0afefabd42394
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/20875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Internal PME is detected when bit PME_B0_STS is set. Following devices
causes internal PME.
- Integrated LAN
- HD Audio/Audio DSP
- SATA
- XHCI ('USB3')
- ME Maskable Host Wake
In SPT, PCIEXPWAK_STS bit isn't getting set due to known bug.
So scan all PCIe RP for PME status bit & update event log accordingly.
BUG=b:36992859
TEST=Build for Soraka, Verify resume due to PME on root port is logged
in elog.
Change-Id: I879a7c332e62ab598942b29d31bad84619b35ea7
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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If IGD PCI device is disabled:
1. BAR for the device will be 0.
2. There is no need to allocate framebuffer for this device.
Some early SOCs don't have GFX model fuse by default hence
we need to add a check to ensure PCI device is enable. This
code to avoid die inside coreboot for missing resources.
Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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As per discussion with CSME team, ME is NOT using PCI Config
Space register HFSTS2 Bit 10 to update ME power-gated status.
ME goes to CM0-PG state after ME device becomes idle after
Bit 2 of MMIO register offset 0x800 (D0i3 Control - HECI1_D0I3C)
is being set.
And to retrieve the PG status of ME, one should read from the
PWRMBASE+offset 0x590 (which should give the value 0xF9) and
PWRMBASE+offset 0x594 (which should give the value 0xFF).
But, also it needs some time for the ME FW to go to idle state
and reflect these values in PWRMBASE registers after D0i3 bit
is being set. This does not happen instantly.
So, in coreboot, if we read the ME PG state in finalize.c, which
happens just after FSP Notify phase, where actually ME D0i3 bit
is set, we do not read the correct PG state values (i.e, 0xF9
and 0xFF).
But, once it boots to Kernel, if we read those same registers
through iotool mmio_read32 command, we get correct values.
So, removing the ME PG state prints from coreboot, since it is
actually showing wrong information, although ME Power Gating is
successful.
Change-Id: Idd31a9803b4c9db7d4bb8bbec5374583a8df0c41
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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init_igd_opregion itself is supposed to return cb_err so this adds
error handling, just like other implentations of write_acpi_tables do it.
this had been found by coverity:
*** CID 1378270: Error handling issues (CHECKED_RETURN)
/src/soc/intel/skylake/igd.c: 147 in write_acpi_igd_opregion()
141 /* If IGD is disabled, exit here */
142 if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF)
143 return current;
144
145 printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
146 opregion = (igd_opregion_t *)current;
CID 1378270: Error handling issues (CHECKED_RETURN)
Calling "init_igd_opregion" without checking return value
(as is done elsewhere 5 out of 6 times).
147 init_igd_opregion(opregion);
148 update_igd_opregion(opregion);
149 current += sizeof(igd_opregion_t);
150 current = acpi_align_current(current);
TEST=Built
Change-Id: If6f5d53037f093607d89cfe8faf193d55de7f6c4
Found-by: Coverity (CID 1378270: Error handling issues (CHECKED_RETURN))
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/20766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The values were verified to be correct with the KabylakeFsp0001 from
github. Skylake FSP documentation disagrees so YMMV.
Change-Id: I1ee04dbbed48d5376dbc24ae70753b059f2646eb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20765
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I2cd210dd0443b854294ce7ee8e267594e3ea1780
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20651
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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As per GCC 7.1 compiler struct reset_reply is considered
as uninitialized inside send_heci_reset_message function.
Change-Id: Ide53a9267dfba1a00263ada1d7016a48ecb9aad8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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coreboot was setting SPI FPR register to protect the
mrc_cache data range stored in flash. This programming was being done
after FSP Notify 1.
But, FSP was locking the SPI by setting FLOCKDN Bit during Notify
phase 1, due to which coreboot was unable to protect that range.
As solution, FSP introduced a new UPD SpiFlashCfgLockDown to skip
the lockdown of flash on interest of bootloader. Set that UPD to 0
to skip the lockdown of FAST_SPI flash from FSP.
The same is being done from coreboot after end of Post at finalize.c
file.
BUG=b:63049493
BRANCH=none
TEST=FPR can be set properly to protect the mrc_cache range. The
issue reported in the bug doesn't come when both software and
hardware WP is enabled with this patch.
Change-Id: I3ffca2f1b05ab2e4ef631275ef7c3a6e23e393aa
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable SOC_INTEL_COMMON_GFX_OPREGION for all FSP versions.
Allows to get rid of opregion.c, as it's no longer needed.
Change-Id: I39190488e12917a09dbf7ee3947a33940ebc290b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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This patch is to provide an additional read LPC pci offset register
BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is
successful.
Change-Id: I308c0622d348fc96c410a04ab4081bb6af98e874
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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LPC pci config register BIOS Control (BC) - offset 0xDC bit 1
is for Lock Down.
Change-Id: I838dd946b8cdb7114f58ccc5d02159f241f0bad0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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`CONFIG_PRE_GRAPHICS_DELAY` was only applied on a dead code path in
`igd.c` that is guarded by always selected `CONFIG_ADD_VBT_DATA_FILE`.
Nobody missed it for nearly a year, plus, it's not applied on the GOP
path, let's drop it.
Change-Id: I0b70cce3a3f2b50cb4e72c4d927b35510ff362a2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This quirk was superseded a view lines above. Also the whole path is
guarded by `CONFIG_ADD_VBT_DATA_FILE` which is always selected for
nearly a year now.
Change-Id: I7fc5184d6e81e4588616e0302dee410e74bdab5a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
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It looks like this code was written with completely different semantics
in mind. Controllers, channels and DIMMs are all presented in their phy-
sical order (i.e. gaps are not closed). So we have to look at the whole
structure and not only the first n respective entries.
Change-Id: I8a9039f73f1befdd09c1fc8e17cd3f6e08e0cd47
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20650
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We've just decided to remove the only known use of the VBSD_SW_WP flag
in vboot (https://chromium-review.googlesource.com/c/575389), since it
was unused and never reliable on all platforms anyway. Therefore, we can
now also remove the coreboot infrastructure that supported it. It
doesn't really hurt anyone, but removing it saves a small bit of effort
for future platforms.
Change-Id: I6706eba2761a73482e03f3bf46343cf1d84f154b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Enable SMBus controller based on config in mainboard devicetree.cb
BUG=None
TEST= Build for Soraka, Verify that SMBus is enabled or disabled (run
lspci in OS) based on board devicetree.cb config 'SmbusEnable'.
Change-Id: I04c8bc30c03fd8dc7cc8ae239885e740b09e9bc1
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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HECI2 and HECI3 devices are “function disable” during FSP
Silicon Init phase. Device will not be visible over PCI bus
hence removing these devices from wake source list.
Change-Id: I0de665e039d74e49e5a22db9714bc9fee734e681
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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It should never be globally exposed. Remove the global symbol
and make it static.
Change-Id: I3b85f3bbf6a73d480cdefdcdec26e137e3a3f75f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
BUG=b:7473486, b:35775024
BRANCH=None
TEST=On bootup make sure PL2 and PsysPL2 values set
properly (through debug output)
Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))
Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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The FSP 2.0 path uses postcar to decompress ramstage. Since postcar
is entirely RAM based there's no need to have an excessively large
stack for the lzma decompression buffer. Therefore, reduce the stack
required to 1 KiB like apollolake.
Change-Id: I45e5c283f8ae87e701c94d6a123463dddde3f221
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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This reverts commit 5535cead (intel/skylake: Disable SaGv in
recovery mode).
Commit 5535cead disables SaGv in recovery mode to save few seconds
booting time as we were doing memory training on every recovery flow.
Now we don't need to perform MRC training on every recovery boot
due to RECOVERY_MRC_CACHE implementation in place. Hence we don't
need to define different SaGv policy between Normal (developer) mode
and recovery mode to save few seconds.
Using different SaGv parameters between recovery and all other mode
has some significent drawbacks over warm reboot cycle. We are seeing
a MRC traning hang in eve/soraka/poppy devices with below use case.
Step 1: Boot system in developer mode (first time RW_MRC training)
Step 2: Set recovery_request=1 (using crossystem) and issue “reboot”
from OS
Step 3: System will perform recovery mode MRC training and boot to
OS (first time RECOVERY_MRC training)
Step 4: Issue “reboot” from OS console.
Step 5: System wil boot in developer mode (using RW_MRC cache)
Step 6: Set recovery_request=1 (using crossystem) and issue “reboot”
from OS
Step 7: System will pick RECOVERY_MRC_CACHE and will hang during
MRC training.
This patch fixes issue mentioned above and ensures system boot to
OS without any hang if we change mode (dev<->recovery) over warm
reset.
BUG=b:63515071
BRANCH=none
TEST=manual stress testing of dev<->recovery mode over warm boot.
No MRC hang with this fix on eve/soraka/poppy devices.
Change-Id: I8d094a8b6d78ea3bf8f929870a4a179495c29c78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Don't need this additional 2ms delay as PCR read after sideband write
help to fix original hard hang issue.
This reverts commit d4b6ac19b0a6619ebe645875282643cc50cf7a3e.
Change-Id: I4232cba5b92e17f728795f7c282af6161e385e9b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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BIOS must ensure to read same PCR offset after PCR write operation
is done.
BUG=b:35587084
BRANCH=eve
TEST=manual stress testing of D0<->D3 transition on eve failing
unit. No hard hang with this fix.
Change-Id: Id3d567aab517b16ff99a526fc29c2d71bf4042d0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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The PMC of PCH-H requires a different destination id.
TEST=Run on kontron/bsl6 and observed that PM registers are correctly
dumped at start of romstage.
Change-Id: I862e4df986f1cdea34f8fa45d016fb6b51f29122
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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Move the generic I/O decode range setup before the console init.
TEST=Run on kontron/bsl6 which requires 0xa80/0xa81 decoded to
initialize serial ports. Serial console works from boot-
block on.
Change-Id: I9829f188c80eb73f6cd91b0c22e1c07da5745ad6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX controls building. The SGX feature
is still enabled from devicetree.cb. As of now this SGX init supports
only KBL (SKL not tested). Support of SGX for new SOCs would be added
incrementally in this common code base.
Change-Id: I0fbba364b7342e686a2287ea1a910ef9a4eed595
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/20173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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This patch basically does two things -
1) Remove unnecessary setting of flex_ratio to TDP nominal:
Factory configured (default) Max Non-TURBO ratio(P1) is already cofigured
in MSR_PLATFORM_INFO(0xCE).
If this Maximum Non-TURBO Ratio(P1) needs to be modified, it should be done
using MSR_FLEX_RATIO (0x194).
Here, in this code, the FLEX_RATIO is being modified by the TDP Nominal
Ratio, reading the MSR_CONFIG_TDP_NOMINAL(0x648). But this value is
actually less than the factory configured Maximum Non TURBO Ratio (P1).
So, this code is actually not required.
Also, the Bit 12 in PCH Soft Strap Register is already set in descriptor.
This Bit implies Processor Boot Max Frequency -
0 = Disable Boot Max Frequency
1 = Enable Boot Max Frequency (Default)
This setting determines if the processor will operate at maximum frequency
at power-on and boot.
Thus this patch will avoid one extra platform warm reset now onwards.
2) Remove wrongly setting Max Frequency in Bootblock phase:
In the function set_max_frequency(), the P-State max ratio was set to
TDP Nominal ratio if C-TDP was enabled, else it was set to Max Non
Trbo ratio.
But, when the cpu gets reset, it will operate with the Max-Non Turbo
ratio only, which is greater than the TDP Nominal ratio.
So, no need to set back the ratio to TDP Nominal which is lower than
the currently operating frequency.
BUG=none
BRANCH=none
TEST=Build and boot poppy
Change-Id: I24bfc86ddf0f038d85da938e41e950382fe2a6c3
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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There is no choice, if not leaving it with the default the build
will fail.
Change-Id: Id91e3ce87f8ced3001fcd2125f8f6781b270f5bc
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Return CB_SUCCESS and CB_ERR instead of some integer.
Preparation to merge intel/soc and intel/nb opregion implementations.
Change-Id: Ib99fcfe347b98736979fc82ab3de48bfc6fc7dcd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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In the D0 and D3 ACPI methods use word access to the PME status and
control register. This brings the code inline with the Intel reference
code and matches how the kernel handles access to this register.
BUG=b:35587084
BRANCH=eve
TEST=manual stress testing of D0<>D3 transition across multiple devices
Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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For the skylake/kabylake generation of PCH there is an ACPI workaround
for emmc/sd power state that involves disabling and re-enabling dynamic
clock gating after enabling power to the controller, before setting the
power state to D0.
Under certain conditions we have observed that the controller is not
powered and ready by the time the kernel attempts to read the PME
control and status register and so the system will hang while attempting
to read PCI config register 0x84.
To ensure that the controller is ready add a 2ms delay after re-enabling
dynamic clock gating and before setting the power state to D0.
This issue has been observed on eMMC, but the same workaround exists for
the SD card interface so the same delay is added there.
BUG=b:35587084
BRANCH=eve
TEST=manual stress testing of D0<>D3 transition across many devices
shows no hard hang after 2 days.
Change-Id: If0f0323cf5437c54c907c332937b5de9dda2d8f6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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As per latest BWG, ucode reloading should be done at the end
of Mp Init, i.e., after PRMRR and other features are enabled.
No reloading specifically after SMM Relocation is required.
As, in the Common CPU MP Init code, we are already doing a
uCode load at the end of MP Init Feature Programming, hence,
the uCode loading after SMM relocation can be removed.
Change-Id: Ib1957c5fe5a8c83bb20b978a9841670b0c3e8846
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch uses the common CPU Mp Init code.
BUG=none
BRANCH=none
TEST=Build and boot poppy
Change-Id: Ieb2f8ae25a31e86e9251fe97859678745fe610f5
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
This patch uses common SCS library to setup
sd card.
Change-Id: I06898e30a9b39f169b35f581a3ee09238f0f40c4
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/20217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Change-Id: Ib7aa495ccfd405d6ffc968388c28dc540da2f525
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
USB port status register can be used to decide if a particular port
was responsible for generating PME# resulting in device wake:
1. CSC bit is set and port is capable of waking on connect/disconnect
2. PLC bit is set and port is in resume state
BUG=b:37088992
TEST=Verified with wake on USB2.0 port 3, mosys shows:
19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3
Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.
This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).
Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.
Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19789
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This patch enables ACPI timer emulation on all the logical cpus.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Verify MSR 0x121 gets programmed on all logical cpus during coreboot MP Init.
Change-Id: I2246cdfe1f60fd359b0a0eda89b4a45b5554dc4a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18288
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch makes SOC files to use common/block/cpu/cpulib.c
file's helper functions.
Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/19566
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FIT is already loading microcode before CPU Reset. So, we need
not update the microcode again in RO FW in bootblock.
But we need to update in RW FW if there is any new ucode version.
So, added the update microcode function in get_microcode_info callback
before MP Init to make sure BSP is using the microcode from cbfs.
BUG=none
BRANCH=none
TEST=Build and Boot poppy
Change-Id: I5606563726c00974f00285acfa435cadc90a085e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20051
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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If the boot media is memory mapped temporarily mark it as write
protect MTRR type so that memory-mapped accesses are faster.
Depthcharge payload loading was sped up by 75ms using this.
Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch perform resource mapping for PCI,
fixed MMIO, DRAM and IMR's based on inputs given by SoC.
TEST=Ensure PCI root bridge 0:0:0 memory resource allocation
remains same between previous implementation and current
implementation.
Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The new config choice is called RUN_FSP_GOP. Some things had to happen
on the road:
* Drop confusing config GOP_SUPPORT,
* Add HAVE_FSP_GOP to chipsets that support it,
* Make running the GOP an option for FSP2.0 by returning 0
in random VBT getters.
Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Remove PCI IDs inclusion from soc header rather referring those
from device/pci_ids.h.
Change-Id: I490da3e336fb6f8194d5fba800132f550ed5ab37
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Place `tdp_pl2_override` above the FSP options as it's not an FSP option.
Change-Id: Idff2b628d19ce1a80294b28c55c05ba4157d07e0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Provide some enums instead of unreadable comments that are usually
copied all over.
Change-Id: Iff551565647f28ecb226e1df633b4deec0ab0a7f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Use timer code from soc/intel/common. This code removes
monotonic timer refrence w.r.t MSR 24Mhz counter(0x637)
and use tsc timer.
Change-Id: I7fad620b11c9e5db128f646639c79ea58a0a574f
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add config for cpu base clock frequency(Mhz) and replace current
refrence from soc/cpu.h with config option.
Change-Id: Idf8e85f7ae6d965fa987a4f5c4905503ee354d69
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/20016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add fast_spi_cache_bios_region() that sets up a variable
MTRR as write-protect covering the fast spi BIOS region.
Change-Id: I282c5173cc655004daf16ea2e85423aaded3648d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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Currently, there is no macro to set GPIO interrupt trigger mode.
The purpose is to make coreboot set same trigger mode as GpioInt
BUG=b:62067569
TEST=checked unused interrupt on SD_CD does not happen after s3 resume
Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/19992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add more fine-grained details about what device caused the PME wake
event. This requires checking the PME status bit (bit 15) in PCI PM
control and status register for the PCI device.
BUG=b:37088992
TEST=Verifed that XHCI wake source was identified correctly:
135 | 2017-05-25 15:28:17 | ACPI Enter | S3
136 | 2017-05-25 15:28:26 | ACPI Wake | S3
137 | 2017-05-25 15:28:26 | Wake Source | PME - XHCI | 0
Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19925
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is required to add wake sources for PCIE PME events.
BUG=b:37088992
Change-Id: Ideecdf133908b0819d7d993e1c7df1a6578cb77d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Implement GPIO ACPI AML generating functions that can be called by
coreboot drivers to generate GPIO manipulation code in AML. Following
API functions are implemented:
1. acpigen_soc_read_rx_gpio
2. acpigen_soc_get_tx_gpio
3. acpigen_soc_set_tx_gpio
4. acpigen_soc_clear_tx_gpio
In addition to the API functions above, helper functions are added to
gpio.asl to set/clear/get Tx value of GPIO.
BUG=b:62028489
Change-Id: I77e5d0decd8929a922d06b02312378f092551667
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19828
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Field Programmable Fuses (FPF) status maintained by
CSME in bits 30:31 of FWSTS6 for Skylake and Kabylake.
FPF committed means CSME has blown the fuses.
Change-Id: If63c7874e6c894749df8100426faca0ad432384b
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/19747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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If deep Sx is enabled and prev sleep state was not S0, then if SUS
power was lost, it means that the platform had entered deep Sx. Add an
elog entry for deep Sx variant in this case.
BUG=b:38436041
TEST=Verified that elog entries are updated correctly:
Deep S5:
59 | 2017-05-19 10:39:08 | Kernel Event | Clean Shutdown
60 | 2017-05-19 10:39:09 | ACPI Enter | S5
61 | 2017-05-19 10:39:17 | System boot | 22
62 | 2017-05-19 10:39:17 | EC Event | Power Button
63 | 2017-05-19 10:39:17 | ACPI Deep Sx Wake | S5
64 | 2017-05-19 10:39:17 | Wake Source | Power Button | 0
65 | 2017-05-19 10:39:17 | Chrome OS Developer Mode
Deep S3:
66 | 2017-05-19 10:40:11 | ACPI Enter | S3
67 | 2017-05-19 10:40:16 | EC Event | Power Button
68 | 2017-05-19 10:40:16 | ACPI Deep Sx Wake | S3
69 | 2017-05-19 10:40:16 | Wake Source | Power Button | 0
Normal S3:
77 | 2017-05-19 10:43:22 | ACPI Enter | S3
78 | 2017-05-19 10:43:39 | EC Event | Power Button
79 | 2017-05-19 10:43:39 | ACPI Wake | S3
80 | 2017-05-19 10:43:39 | Wake Source | Power Button | 0
Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use SATA common code from soc/intel/common/block/sata
and clean up code.
Change-Id: Ib5d65f1afda6b2f8098f1c006623a48cf2690593
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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In the intel/common/block
* Move I2C common code from intel/common to intel/common/block.
* Split the code into common, early init and post mem init stages and put it
in lpss_i2c.c, i2c_early.c and i2c.c respectively.
* Declare functions for getting platform specific i2c bus config and
mapping bus to devfn and vice versa, that have to be implemented by SoC.
In skylake/apollolake
* Stop using code from soc/intel/common/lpss_i2c.c.
* Remove early i2c initialization code from bootblock.
* Refactor i2c.c file to implement SoC specific methods
required by the I2C IP block.
Change-Id: I4d91a04c22e181e3a995112cce6d5f0324130b81
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/19468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Set MSR 0x1A0 bit[16] based on EIST config option.
Default Hardware Managed P-state (HWP) also known as Intel Speed Shift
is enabled on SKL hence disable EIST and ACPI P-state table.
Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Program C3/C7/C10 interrupt response time for all cores.
Change-Id: I4f47502e1c212118d7cc89d4de60a1854072964a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I53ed687dc49524e001889f091825b2cc530546a3
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I2ca32ab594552424e4f1358302641f159a3d7e62
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change a4b11e5c90 (soc/intel/skylake: Perform CPU MP Init
before FSP-S Init) dropped mtrr_check while re-organizing
code. Add the check back after MTRR setup is performed.
BUG=b:36656098
TEST=Verified that MTRR check is done after setup on poppy.
Change-Id: I440405c58c470ffa338be386d84870635530a031
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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With change a4b11e5c90 (soc/intel/skylake: Perform CPU MP Init
before FSP-S Init) to perform CPU MP init before FSP-S init, MTRR
programming was moved to be performed after CPU init is done. However,
in order to allow callbacks after MP init, PARALLEL_MP_AP_WORK needs
to be enabled. Since this option was not selected, MTRR programming
always failed in ramstage for Skylake / Kaby Lake mainboards.
BUG=b:36656098
TEST=Verified 2500+ cycles of suspend resume on poppy.
Change-Id: I22a8f6ac90ba35075ff97dd57bab66c129f3e771
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The southbridge_trigger_smi() and southbridge_clear_smi_status()
functions are unused. Remove them.
Change-Id: I86994191a63cbf515bc330433ef7c3f79a39936e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Now that we have a common block driver for fast spi flash controller,
provide spi_ctrlr structure that can be used by different platforms
for defining the bus-ctrlr mapping. Only cs 0 is considered valid.
Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The current implementation is incorrect and is
actually disabling the ports. Fixes that.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that we can boot from
SATA SSD.
Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19553
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Remove struct skylake_i2c_config from chip.h since it is not used
anymore.
Change-Id: Icde4b7af5b9c31020099c1a6372a6867827f61ae
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This changelist adds the 48Khz 2ch 16bit NHLT configuration for the
Maxim 98927 speaker amplifier codec.
BUG=b:35585307
TEST=manual testing to ensure speaker output is functional on Eve board
Change-Id: Ieda988b557ecefdace5f81b474a952af56e69315
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19548
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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