diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-05-02 19:43:20 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-05-05 23:40:51 +0200 |
| commit | f1db5fdb4d03b4766cf23e4b04a05b0fc05586a0 (patch) | |
| tree | cd4d04900e1b5d3e27d4d13cdfa39297e661e2aa /src/soc/intel/skylake | |
| parent | 35418f9814a64073550eb63a3bcb2e79021347cb (diff) | |
soc/intel/common: Provide common block fast_spi_flash_ctrlr
Now that we have a common block driver for fast spi flash controller,
provide spi_ctrlr structure that can be used by different platforms
for defining the bus-ctrlr mapping. Only cs 0 is considered valid.
Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/spi.c | 19 |
1 files changed, 2 insertions, 17 deletions
diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c index e11e13f763..e575e6e265 100644 --- a/src/soc/intel/skylake/spi.c +++ b/src/soc/intel/skylake/spi.c @@ -20,28 +20,13 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/spi.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <soc/ramstage.h> #include <spi-generic.h> -/* SPI controller managing the flash-device SPI. */ -static int flash_spi_ctrlr_setup(const struct spi_slave *dev) -{ - if ((dev->bus != 0) || (dev->cs != 0)) { - printk(BIOS_ERR, "%s: Unsupported device bus=0x%x,cs=0x%x!\n", - __func__, dev->bus, dev->cs); - return -1; - } - - return 0; -} - -static const struct spi_ctrlr flash_spi_ctrlr = { - .setup = flash_spi_ctrlr_setup, -}; - const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { .ctrlr = &flash_spi_ctrlr, .bus_start = 0, .bus_end = 0 }, + { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 }, #if !ENV_SMM { .ctrlr = &gspi_ctrlr, .bus_start = 1, .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)}, |