summaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake
AgeCommit message (Collapse)Author
2017-06-13Consolidate reset API, add generic reset_prepare mechanismJulius Werner
There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Also remove cpu_reset() completely since it's not used anywhere and doesn't seem very useful compared to the others. Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19789 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-09soc/intel/skylake: Enable ACPI PM timer emulation on all CPUsSubrata Banik
This patch enables ACPI timer emulation on all the logical cpus. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Verify MSR 0x121 gets programmed on all logical cpus during coreboot MP Init. Change-Id: I2246cdfe1f60fd359b0a0eda89b4a45b5554dc4a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18288 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/intel/skylake: Use CPU common library codeBarnali Sarkar
This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19566 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/intel/skylake: Move update microcode from cbfs to mp_ops callbacksBarnali Sarkar
FIT is already loading microcode before CPU Reset. So, we need not update the microcode again in RO FW in bootblock. But we need to update in RW FW if there is any new ucode version. So, added the update microcode function in get_microcode_info callback before MP Init to make sure BSP is using the microcode from cbfs. BUG=none BRANCH=none TEST=Build and Boot poppy Change-Id: I5606563726c00974f00285acfa435cadc90a085e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20051 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-06-09soc/intel/skylake: Cache the MMIO BIOS regionAaron Durbin
If the boot media is memory mapped temporarily mark it as write protect MTRR type so that memory-mapped accesses are faster. Depthcharge payload loading was sped up by 75ms using this. Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-09soc/intel/skylake: Use common systemagent codeSubrata Banik
This patch perform resource mapping for PCI, fixed MMIO, DRAM and IMR's based on inputs given by SoC. TEST=Ensure PCI root bridge 0:0:0 memory resource allocation remains same between previous implementation and current implementation. Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/skylake: add ACPI method to generate USB port infoMatt DeVillier
Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-08fsp/gop: Add running the GOP to the choice of gfx initNico Huber
The new config choice is called RUN_FSP_GOP. Some things had to happen on the road: * Drop confusing config GOP_SUPPORT, * Add HAVE_FSP_GOP to chipsets that support it, * Make running the GOP an option for FSP2.0 by returning 0 in random VBT getters. Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-06soc/intel/skylake: Use PCI IDs from device/pci_ids.hSubrata Banik
Remove PCI IDs inclusion from soc header rather referring those from device/pci_ids.h. Change-Id: I490da3e336fb6f8194d5fba800132f550ed5ab37 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-06soc/intel/skylake/chip.h: Reorder declarationsNico Huber
Place `tdp_pl2_override` above the FSP options as it's not an FSP option. Change-Id: Idff2b628d19ce1a80294b28c55c05ba4157d07e0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-06soc/intel/skylake/chip.h: Provide some enumsNico Huber
Provide some enums instead of unreadable comments that are usually copied all over. Change-Id: Iff551565647f28ecb226e1df633b4deec0ab0a7f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-05soc/intel/skylake: Use Intel timer common codeAamir Bohra
Use timer code from soc/intel/common. This code removes monotonic timer refrence w.r.t MSR 24Mhz counter(0x637) and use tsc timer. Change-Id: I7fad620b11c9e5db128f646639c79ea58a0a574f Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-05soc/intel/skylake: Add config for cpu base clock frequencyAamir Bohra
Add config for cpu base clock frequency(Mhz) and replace current refrence from soc/cpu.h with config option. Change-Id: Idf8e85f7ae6d965fa987a4f5c4905503ee354d69 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/20016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-05soc/intel/common/block: add bios caching to fast spi moduleAaron Durbin
Add fast_spi_cache_bios_region() that sets up a variable MTRR as write-protect covering the fast spi BIOS region. Change-Id: I282c5173cc655004daf16ea2e85423aaded3648d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-03soc/intel/skylake: Add macro for setting GPIO interrupt trigger mode.Kane Chen
Currently, there is no macro to set GPIO interrupt trigger mode. The purpose is to make coreboot set same trigger mode as GpioInt BUG=b:62067569 TEST=checked unused interrupt on SD_CD does not happen after s3 resume Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/19992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-27soc/intel/skylake: Add detailed information about PME wake sourcesFurquan Shaikh
Add more fine-grained details about what device caused the PME wake event. This requires checking the PME status bit (bit 15) in PCI PM control and status register for the PCI device. BUG=b:37088992 TEST=Verifed that XHCI wake source was identified correctly: 135 | 2017-05-25 15:28:17 | ACPI Enter | S3 136 | 2017-05-25 15:28:26 | ACPI Wake | S3 137 | 2017-05-25 15:28:26 | Wake Source | PME - XHCI | 0 Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19925 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-27soc/intel/skylake: Add missing PCH_DEV_PCIE* definitionsFurquan Shaikh
This is required to add wake sources for PCIE PME events. BUG=b:37088992 Change-Id: Ideecdf133908b0819d7d993e1c7df1a6578cb77d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-25soc/intel/skylake: Implement GPIO ACPI AML generating functionsFurquan Shaikh
Implement GPIO ACPI AML generating functions that can be called by coreboot drivers to generate GPIO manipulation code in AML. Following API functions are implemented: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio In addition to the API functions above, helper functions are added to gpio.asl to set/clear/get Tx value of GPIO. BUG=b:62028489 Change-Id: I77e5d0decd8929a922d06b02312378f092551667 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19828 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-22soc/intel/skylake: Display FPF status of CSMEPratik Prajapati
Field Programmable Fuses (FPF) status maintained by CSME in bits 30:31 of FWSTS6 for Skylake and Kabylake. FPF committed means CSME has blown the fuses. Change-Id: If63c7874e6c894749df8100426faca0ad432384b Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/19747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-22soc/intel/skylake: Add entry for deep Sx wakeFurquan Shaikh
If deep Sx is enabled and prev sleep state was not S0, then if SUS power was lost, it means that the platform had entered deep Sx. Add an elog entry for deep Sx variant in this case. BUG=b:38436041 TEST=Verified that elog entries are updated correctly: Deep S5: 59 | 2017-05-19 10:39:08 | Kernel Event | Clean Shutdown 60 | 2017-05-19 10:39:09 | ACPI Enter | S5 61 | 2017-05-19 10:39:17 | System boot | 22 62 | 2017-05-19 10:39:17 | EC Event | Power Button 63 | 2017-05-19 10:39:17 | ACPI Deep Sx Wake | S5 64 | 2017-05-19 10:39:17 | Wake Source | Power Button | 0 65 | 2017-05-19 10:39:17 | Chrome OS Developer Mode Deep S3: 66 | 2017-05-19 10:40:11 | ACPI Enter | S3 67 | 2017-05-19 10:40:16 | EC Event | Power Button 68 | 2017-05-19 10:40:16 | ACPI Deep Sx Wake | S3 69 | 2017-05-19 10:40:16 | Wake Source | Power Button | 0 Normal S3: 77 | 2017-05-19 10:43:22 | ACPI Enter | S3 78 | 2017-05-19 10:43:39 | EC Event | Power Button 79 | 2017-05-19 10:43:39 | ACPI Wake | S3 80 | 2017-05-19 10:43:39 | Wake Source | Power Button | 0 Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-22soc/intel/skylake: Use Intel SATA common codeAamir Bohra
Use SATA common code from soc/intel/common/block/sata and clean up code. Change-Id: Ib5d65f1afda6b2f8098f1c006623a48cf2690593 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-22soc/intel/skylake: Use Intel PCIe common codeAamir Bohra
Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-18intel/common/block/i2c: Add common block for I2C and use the same in SoCsRizwan Qureshi
In the intel/common/block * Move I2C common code from intel/common to intel/common/block. * Split the code into common, early init and post mem init stages and put it in lpss_i2c.c, i2c_early.c and i2c.c respectively. * Declare functions for getting platform specific i2c bus config and mapping bus to devfn and vice versa, that have to be implemented by SoC. In skylake/apollolake * Stop using code from soc/intel/common/lpss_i2c.c. * Remove early i2c initialization code from bootblock. * Refactor i2c.c file to implement SoC specific methods required by the I2C IP block. Change-Id: I4d91a04c22e181e3a995112cce6d5f0324130b81 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/19468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-16soc/intel/skylake: Add option to enable/disable EISTSubrata Banik
Set MSR 0x1A0 bit[16] based on EIST config option. Default Hardware Managed P-state (HWP) also known as Intel Speed Shift is enabled on SKL hence disable EIST and ACPI P-state table. Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-16soc/intel/skylake: Configure C-state interrupt response timeSubrata Banik
Program C3/C7/C10 interrupt response time for all cores. Change-Id: I4f47502e1c212118d7cc89d4de60a1854072964a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-09soc/intel/skylake: Use common/blocks/uart codeAamir Bohra
Change-Id: I53ed687dc49524e001889f091825b2cc530546a3 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-09soc/intel/skylake: Use intel/common/block/smbus codeAamir Bohra
Change-Id: I2ca32ab594552424e4f1358302641f159a3d7e62 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-08soc/intel/skylake: Enable MTRR checkFurquan Shaikh
Change a4b11e5c90 (soc/intel/skylake: Perform CPU MP Init before FSP-S Init) dropped mtrr_check while re-organizing code. Add the check back after MTRR setup is performed. BUG=b:36656098 TEST=Verified that MTRR check is done after setup on poppy. Change-Id: I440405c58c470ffa338be386d84870635530a031 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-08soc/intel/skylake: Enable PARALLEL_MP_AP_WORKFurquan Shaikh
With change a4b11e5c90 (soc/intel/skylake: Perform CPU MP Init before FSP-S Init) to perform CPU MP init before FSP-S init, MTRR programming was moved to be performed after CPU init is done. However, in order to allow callbacks after MP init, PARALLEL_MP_AP_WORK needs to be enabled. Since this option was not selected, MTRR programming always failed in ramstage for Skylake / Kaby Lake mainboards. BUG=b:36656098 TEST=Verified 2500+ cycles of suspend resume on poppy. Change-Id: I22a8f6ac90ba35075ff97dd57bab66c129f3e771 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-08soc/intel/skylake: remove unused SMI functionsAaron Durbin
The southbridge_trigger_smi() and southbridge_clear_smi_status() functions are unused. Remove them. Change-Id: I86994191a63cbf515bc330433ef7c3f79a39936e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-05soc/intel/common: Provide common block fast_spi_flash_ctrlrFurquan Shaikh
Now that we have a common block driver for fast spi flash controller, provide spi_ctrlr structure that can be used by different platforms for defining the bus-ctrlr mapping. Only cs 0 is considered valid. Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19575 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-05soc/intel/skylake: Enable SATA portsShelley Chen
The current implementation is incorrect and is actually disabling the ports. Fixes that. BUG=b:37486021, b:35775024 BRANCH=None TEST=reboot and ensure that we can boot from SATA SSD. Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19553 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-04soc/intel/skylake: Remove unused skylake_i2c_config structureFurquan Shaikh
Remove struct skylake_i2c_config from chip.h since it is not used anymore. Change-Id: Icde4b7af5b9c31020099c1a6372a6867827f61ae Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-05-04intel/skylake: nhlt: Add 48Khz 2ch 16bit config for max98927Duncan Laurie
This changelist adds the 48Khz 2ch 16bit NHLT configuration for the Maxim 98927 speaker amplifier codec. BUG=b:35585307 TEST=manual testing to ensure speaker output is functional on Eve board Change-Id: Ieda988b557ecefdace5f81b474a952af56e69315 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19548 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-02soc/intel/skylake: Clean up code by using common FAST_SPI moduleBarnali Sarkar
This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19055 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-02soc/intel/skylake: Set xtal bypass on low power idleNaresh G Solanki
When using Wake On Voice &/or DCI, it requires xtal to be active during low power idle. With xtal being active in S0ix state power impact is 1-2 mW. Hence set xtal bypass bit in CIR31C for low power idle entry. TEST= Build with s0ix enable for Poppy. Boot to OS & verify that bit 22 of CIR31C register is set. s0ix works. Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19442 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-01soc/intel/skylake: Add ID for Fizz i7Shelley Chen
Bug=b:35775024 BRANCH=None TEST=boot up successfully to kernel on Fizz i7 sku Change-Id: Iccf9fbef1333f3fea78091b679c2676411559987 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19486 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-28soc/intel/skylake: Use ITSS common codeBora Guvendik
This patch uses common ITSS library to setup itss irq. Change-Id: Ibe65a92f1604277bec229c67f4375b6636c0972d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/19244 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28intel/skylake: Switch FADT to ACPI version 3.0Werner Zeh
On Apollo Lake it was discovered that our current FADT implementation is valid for ACPI version 3.0 but misses fields for ACPI version 5.0. We run into booting issues with Windows 10 using version 5 in the FADT header. In commit 2b8552f49bc3a7d0290f96a84b573669de396011 (intel/apollolake: Switch FADT to ACPI version 3.0) we go back to version 3 for Apollo Lake. Skylake is now the last platform that uses version 5 in FADT header. Change-Id: I2d0367fae5321dee4ccac417b7f99466f8973577 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/19453 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-25soc/intel: Unify `timestamp.inc`Paul Menzel
These files are actually indentical, but unfortunately, the formatting was changed without caring for the already present files. Fix that. Use the license formatting where less lines are used. The next step is to put that in a common location. Change-Id: Iecb263b9d321a33e64988b315220893df2e0045c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/19423 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-25soc/intel/skylake: Fix the PCI ID for SATA controllerFurquan Shaikh
Update the PCI ID for SATA controller on Kaby Lake. Change-Id: Id0b5e0366e04fbac6a57a15407f33f390a2a1856 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19395 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-25soc/intel/skylake: use postcar stage for fsp 2.0Aaron Durbin
Utilize the postcar stage for tearing down CAR and initializing the MTRRs once ram is up. This flow is consistent with apollolake and allows CAR_GLOBAL variables to be directly accessed and no need for migrating CAR_GLOBAL variables as romstage doesn't run with and without CAR being available. Change-Id: I76de447710ae1d405886eb9420dc4064aa26eccc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19335 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-25lib: provide clearer devicetree semanticsAaron Durbin
The devicetree data structures have been available in more than just ramstage and romstage. In order to provide clearer and consistent semantics two new macros are provided: 1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE 2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST The ROMSTAGE_CONST attribute is used in the source code to mark the devicetree data structures as const in early stages even though it's not just romstage. Therefore, rename the attribute to DEVTREE_CONST as that's the actual usage. The only place where the usage was not devicetree related is console_loglevel, but the same name was used for consistency. Any stage that is not ramstage has the const C attribute applied when DEVTREE_CONST is used. Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19333 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-24soc/intel/skylake: Add ID's for Kabylake-RNaresh G Solanki
Add CPUID, IGD, MCH & LPC ID of Kabylake-R. Change-Id: I5ee7b3a2616f71137bba83c071288dbda2acde3d Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19218 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-19soc/intel/skylake: Add ASL entries for IMGU and CIO2 devicesSowmya
Add ASL entries for IMGU and CIO2 devices * _CCA ACPI object to report that there is no Cache Coherent DMA support. * CAMD ACPI object to specify the device type. These ACPI objects are used by Intel kernel drivers. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that DSDT table has the entries for IMGU and CIO2 devices. Change-Id: I13050253e18408cdb1e196f8003b3f43299aa5a5 Signed-off-by: Sowmya V <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18968 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13soc/intel/skylake: Split AC/DC settings for Deep Sx configDuncan Laurie
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled in both DC and AC states. However since using Deep S3 disables some expected features like wake-on-USB it is not always desired to enable the same state in both modes. To address this split the setting and add a separate config for Deep Sx in AC and DC states. All motherboards that set this config were updated, but there is no actual change in behavior in this commit. BUG=b:36723679 BRANCH=none TEST=This commit has no runtime visible changes, I verified on Eve that the Deep SX config registers are unchanged, and it compiles for all affected boards. Change-Id: I590f145847785b5a7687f235304e988888fcea8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19239 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-11soc/intel/skylake: Use intel/common/uart driverAamir Bohra
Change-Id: Id132df15ae5a6aef75d6434df18fc71d8d28c3ca Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19003 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11soc/intel/skylake: Use LPSS common libraryAamir Bohra
Use lpss common library to program reset and clock register for lpss modules. Change-Id: I198feba7c6f6d033ab77ed25a5bd9ea99411a1e4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19153 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10soc/intel/skylake: Use RTC common codeSubrata Banik
This patch uses common RTC library to enable upper 128 byte bank of RTC RAM. Change-Id: Ibcbaf5061e96a67815116a9f7a03be515997be6d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18701 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-10soc/intel/skylake: Use common PCR moduleSubrata Banik
This patch use common PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pcr_ids.h Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-07soc/intel/skylake: Enable XHCI clock gate control in ACPINaresh G Solanki
Enable SS link trunk clock gating & D3hot when device enters D3 state. Similarly disable SS link trunk clock gating & D3hot when device enters D0 state TEST=Build & boot Poppy board. Check working for XHCI wake when DUT is in S3. Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/18879 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-06soc/intel/skylake: Add support for GSPI controllerFurquan Shaikh
Sky Lake PCH contains two GSPI controllers. Using the common GSPI controller driver implementation for Intel PCH, add support for GSPI controller buses on Sky Lake/Kaby Lake. BUG=b:35583330 Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19099 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05soc/intel/lpss: Provide common LPSS clock configFurquan Shaikh
Since there are multiple controllers in the LPSS and all use the same frequency, provide a single Kconfig option for LPSS_CLOCK_MHZ. BUG=b:35583330 Change-Id: I3c0cb62d56916e6e5f671fb5f40210f4cb33316f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19115 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-05soc/intel/skylake: Add tsc_freq.c to verstageFurquan Shaikh
This is required to provide tsc freq required by timer library. BUG=b:35583330 TEST=Verified that delay(5) in verstage adds a delay of 5 seconds. Change-Id: I03edebe394522516b46125fae1a17e9a06fd5f45 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19094 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by defaultJulius Werner
The virtualized developer switch was invented five years ago and has been used on every vboot system ever since. We shouldn't need to specify it again and again for every new board. This patch flips the Kconfig logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the latter for Lumpy which seems to have been omitted incorrectly, and hide it from menuconfig since it's a hardware parameter that shouldn't be configurable.) Since almost all our developer switches are virtual, it doesn't make sense for every board to pass a non-existent or non-functional developer mode switch in the coreboot tables, so let's get rid of that. It's also dangerously confusing for many boards to define a get_developer_mode() function that reads an actual pin (often from a debug header) which will not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set. Therefore, this patch removes all those non-functional instances of that function. In the future, either the board has a physical dev switch and must define it, or it doesn't and must not. In a similar sense (and since I'm touching so many board configs anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC. Instead, it should just be assumed by default whenever a Chrome EC is present in the system. This way, it can also still be overridden by menuconfig. CQ-DEPEND=CL:459701 Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18980 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28soc/intel/skylake: Clean up code by using common System Agent moduleSubrata Banik
This patch currently contains the SA initialization required for bootblock phase - 1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code. 2. Perform PCIEXBAR programming based on soc configurable PCIEX_LENGTH_xxxMB 3. Use common systemagent header file. Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18566 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28soc/pci_devs.h: Use consistent naming in soc/pci_devs.hSubrata Banik
This patch to make common PCI device name between APL and SKL. Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28soc/intel/common/block: Add cache as ram init and teardown codeSubrata Banik
Create sample model for common car init and teardown programming. TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED and CAR_NEM configs till post code 0x2a. Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18381 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-24soc/intel/skylake: Use C entry code for MTRR programmingSubrata Banik
Make skylake cache as ram SPI mapped MTRR programming align with apollolake code. Change-Id: I87a5c655da8ff5f6d8ef86907b7ae2263239b1ac Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18923 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-23soc/intel/skylake: Add SGX initializationRobbie Zhang
This patch implements SGX initialization steps in coreboot per Intel SGX BWG rev 2.0.8 for Kaby Lake SoC. If enabled on a Kabylake device, SoC capability and PRM (processor reserved memory) of desired size (needs to be configured through PrmrrSize) are provisioned for later software stack to use SGX (i.e., run SGX enclaves). One issue is still puzzling and needs to be addressed: by calling configure_sgx() in cpu_core_init() which is the per-thread function, SGX is always failing for thread 0 but is successful for other 3 threads. I had to call configure_sgx() again from soc_init_cpus() which is the BSP-only function to make it enable on the BSP. Another pending work is the implementation for the Owner Epoch update which shall be added later. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve, verified SGX activation is successful on all threads. Change-Id: I8b64284875eae061fa8e7a01204d48d320a285a9 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18445 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-22soc/intel/skylake: Add option to disable host reads to PMC XRAMRizwan Qureshi
FSP disables host access to shadowed PMC XRAM registers by default, it also provides a UPD to enable/disable host reads to these regiters. Expose the same in devicetree as a config option. Change-Id: Iaa33aa3233bda4f050da37d1d8af0556311c9496 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18319 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-22soc/intel/skylake: Add configs for enabling DCI and TraceHubAamir Bohra
Add configs for enabling Intel TraceHub and DCI for aid in debugging. Change-Id: Ic40f9499c0125070049856e242e89024ca5a1c4e Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18791 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17soc/intel/skylake: Fix remaining issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible ERROR: Macros with complex values should be enclosed in parentheses ERROR: "foo * bar" should be "foo *bar" ERROR: space required before the open parenthesis '(' ERROR: spaces required around that '=' (ctx:VxW) WARNING: space prohibited between function name and open parenthesis '(' WARNING: storage class should be at the beginning of the declaration WARNING: char * array declaration might be better as static const WARNING: please, no space before tabs WARNING: braces {} are not necessary for single statement blocks WARNING: else is not generally useful after a break or return WARNING: static const char * array should probably be static const char * const TEST=Build for glados Change-Id: Ic14ca3abd193cfe257504a55ab6b74782b26bf6d Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18868 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-17soc/intel/skylake: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch: WARNING: line over 80 characters TEST=Build for glados Change-Id: I79341f46ca06ac052f987975ccaf975470d27806 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18867 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2017-03-17soc/intel/skylake: Add int to unsignedLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build for glados Change-Id: Idc2ad265e8ed8cd7fd6d228cfbe4cbbcb9d3ebfc Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18866 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-15intel/skylake: Support for setting AC/DC loadlineDuncan Laurie
Add options to set the AC and DC loadline values for each supported VR type so these can be tuned on a per-board basis in devicetree.cb. BUG=b:36228330 BRANCH=none TEST=Build and boot on Eve and check debug FSP output to ensure that it is applying the provided loadline values Change-Id: I2a5533d2c9fd86351c86584e3738e80ac4c1f915 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18819 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-15intel/skylake: Fix bug in VR configuration with FSP 2.0Duncan Laurie
With the move to FSP 2.0 the number of VR types supported was reduced to 4, and the VR_RING type is no longer present. This means all existing boards using FSP 2.0 are incorrectly passing VR configuration into FSP as the values corresponding to "GT Sliced" and "GT Unsliced" have changed. Fix this by updating the skylake SOC VR handling to account for changes in the FSP configuration and no longer provide VR_RING type when using FSP 2.0. BUG=b:36228330 BRANCH=none TEST=manual: build and boot on Eve Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-03-15intel/skylake: nhlt: Add support for rt5514 NHLT blobDuncan Laurie
Add support for describing the NHLT blob for the rt5514 DSP. Currently this only supports 4 channel capture. BUG=b:35585307 BRANCH=none TEST=build and boot on Eve P1 Change-Id: Ib59b56222f9aa65370fdcf9ddf25145c571b1b2e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18816 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-14soc/intel/skylake: Extract DIMM Information from FSP MEM INFO HOBBarnali Sarkar
Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB and save it in CBMEM. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in SMBIOS Table from Kernel command "dmidecode". Change-Id: I593d4ccb0d4866e99913a73c49b2f000b51827d1 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18275 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-10soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controllersowmyav
eMMC Controller is taking over 100ms to resume during runtime which results in I/O latency issues on the Skylake systems like Cave and Caroline. This patch adds _DSM method for eMMC comtroller for specifying the device readiness durations. Function index 9 returns package of five integers to set D3 cold delay to zero and ACPI constant Ones for the elements where overriding the default values is not desired. BUG=b:35774937 BRANCH=none TEST=update caroline coreboot and test i/o latency is under 100ms Change-Id: Iacc8aa8560897da8770fe559ca8cd17aaf6ebeba Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/18532 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-09soc/intel/skylake: Add GPIO macros for IOxAPIC and SCILi Cheng Sooi
Add two GPIO macros: 1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the APIC with input assuming the events are edge triggered. 2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose input to SCI assuming the events are level triggered. Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com> Reviewed-on: https://review.coreboot.org/18533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09soc/intel/skylake: Add SKL SOC PCH H GPIO supportLi Cheng Sooi
Add SKL/KBL PCH-H GPIO settings referring from SKL PCH-H specifications to support sklrvp11. Split the gpio_defs.h into headers gpio_pch_h_defs.h and gpio_soc_defs.h for PCH-H specific and SOC specific GPIO defs respectively. Change-Id: I5eaf8d809a1244a56038cbfc29502910eb90f9f2 Signed-off-by: Li Cheng Sooi <li.cheng.sooi@intel.com> Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com> Reviewed-on: https://review.coreboot.org/18027 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-08intel/skylake: Filter suspend well power failure event for Deep SxDuncan Laurie
If Deep Sx is enabled the event log will get entries added on every power sequence transition indicating that the suspend well has failed. When a board is using Deep Sx by design this is intended behavior and just fills the logs with extraneous events. To make this work the device init state has to be executed first so it actually enables the Deep Sx policies in the SOC since this code does not have any hooks back into the devicetree to read the intended setting from there. BUG=b:36042662 BRANCH=none TEST=Perform suspend/resume on Eve device with Deep S3 enabled, and then check the event log to be sure that it does not contain the "SUS Power Fail" event. Change-Id: I3c8242baa63685232025e1dfef5595ec0ec6d14a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18664 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-08intel/skylake: Add function to read state of Deep S5Duncan Laurie
Add a function to read the current state of Deep S5 configuration and indicate if it is enabled (for AC and/or DC) or disabled. This is similar to the existing function that checks Deep S3 enable state. BUG=b:36042662 BRANCH=none TEST=tested with subsequent commits to check Deep S5 state at boot and filter event log messages if it is enabled. Change-Id: I4b60fb99a99952cb3ca6be29f257bb5894ff5a52 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18663 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-08intel/skylake: Add devicetree settings for acoustic noise mitigationDuncan Laurie
Add options to the skylake chip config that will allow tuning the various settings that can affect acoustics with the CPU and its VRs. These settings are applied inside FSP, and they can adjust the slew slew rate when changing voltages or disable fast C-state ramping on the various CPU VR rails. BUG=b:35581264 BRANCH=none TEST=these are currently unused, but I verified that enabling the options can affect the acoustics of a system at runtime. Change-Id: I6a8ec0b8d3bd38b330cb4836bfa5bbbfc87dc3fb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18662 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-06soc/intel/skylake: Clean up CPU codeSubrata Banik
Use header (soc/intel/common/block/include/intelblocks/msr.h) for MSR macros Change-Id: I401b92cda54b6140f2fe23a6447dad89879a5ef0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18554 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06soc/intel/skylake: Use intel/common/xhci driverSubrata Banik
Change-Id: I7bd83d293fcc1848f6f64526d8f38d010c1f69a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18223 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06soc/intel/skylake: Clean up XHCI codeSubrata Banik
Don't need "skylake/include/soc/xhci.h", hence removed. Change-Id: I35df2003f311b557b622ce1d7a1c2e832693c2fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18508 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-04soc/intel/skylake: indicate voltage margining enabled/disabledRizwan Qureshi
Support for voltage margining is dependent on the platform. Enabling voltage margining puts additional constraints for the SLP_S0# to be asserted and hence moving to S0ix state. If the platform PMIC/VR supports PCH voltage reduction, voltage marigining can be enabled. Use the UPD provided by FSP to enable/disable voltage margining. Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18469 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-23soc/intel/skylake: Enable Systemagent IMGURizwan Qureshi
Camera and Imaging device should be enabled for camera usecase, FSP provides a UPD to enable/disable the SA IMGU (Imaging Unit) expose the same as a config option in devicetree.cb Also remove a redundant assignment for PchCio2Enable. BUG=None BRANCH=None TEST=lspci should list 00:05:00 Change-Id: I4cf7daf41bfaf4dcba414921cac2e7e12bf89f37 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18365 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-22acpi: Add ACPI_ prefix to IRQ enum and struct namesFurquan Shaikh
This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-22soc/intel/skylake: Fix broken suspend-resumeFurquan Shaikh
With recent change (a4b11e5c90: soc/intel/skylake: Perform CPU MP Init before FSP-S Init) to perform CPU MP init before FSP-S init, suspend resume is currently broken for all skylake/kabylake boards. All the skylake/kabylake boards store external stage cache in TSEG, which is relocated post MP-init. Thus, if FSP loading and initialization is done after MP-init, then ramstage is not able to: 1. Save FSP component in external stage cache during normal boot, and 2. Load FSP component from external stage cache during resume In order to fix this, ensure that FSP loading happens separately from FSP initialization. Add fsp_load callback for pre_mp_init which ensures that the required FSP component is loaded/saved from/to external stage cache. BUG=chrome-os-partner:63114 BRANCH=None TEST=Verified that 100 cycles of suspend/resume worked fine on poppy. Change-Id: I5b4deaf936a05b9bccf2f30b949674e2ba993488 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18414 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20soc/intel/skylake: Expand USB OC pins definition to support PCH-HTeo Boon Tiong
Currently the USB OC pins definition only being defined up to OC3. For PCH-H, OC4 and OC5 are needed, so add both into OC pin enum. Changes is being verified and booted to Yocto with Saddle Brook. Change-Id: Idaed6fa7dcddb9c688966e8bc59f656aec2b26eb Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/18364 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-19soc/intel/skylake: Disable s0ix if not enabled in devicetreeDuncan Laurie
There is an enable_s0ix config option in the devicetree that should be used to disable it when not set: - do not export C8/C9/C10 C-states in _CST - do not enable SLP_S0 in FSP BUG=chrome-os-partner:58666 TEST=test on eve board to ensure that OS only sees 3 ACPI C-states instead of 6 and that it no longer attempts to enter C10 Change-Id: I90e4dc776d1d17d0b700cda63c8476786cd2e4ff Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18394 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-18soc/intel/skylake: add PrmrrSize to chip configRobbie Zhang
Prmrr configuration is supported by Kabylake FSP-M with UPD provided. It is required as one of the SGX initialization steps in BIOS. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set size and boot. Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18361 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-17soc/intel/skylake: Add Maxim 98927 and Realtek 5663 NHLT blob supportRizwan Qureshi
Add APIs and required parameters for creating Maxim 98927 and Realtek 5336 SSP endpoints in NHLT table. BUG=chrome-os-partner:62051 BRANCH=None TEST=check that NHLT table created is created properly Change-Id: Ica302aab05c5364faf4923dc5327be8e8eaae8b4 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: M Naveen <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/18213 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-17soc/intel/skylake: Add config option for KabylakeRizwan Qureshi
Currently there is no distinction between mainboards using Skylake or Kabylake SoC, Add a config option for Kabylake SoC to allow mainboards to explicitly select if they are using it. Change-Id: Ie7960bd81f88a223894afe3115ddc0bc637e4be4 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18312 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-17intel/skylake: add function is_secondary_thread()Robbie Zhang
There are MSRs that are programmable per-core not per-thread, so add a function to check whether current executing CPU is a primary core or a "hyperthreaded"/secondary core. For instance when trying to program Core PRMRR MSRs(per-core) with mp_init, cpu exception is thrown from the secondary thread. This function was used to avoid that. Potentially this function can be put to common code or arch/x86 or cpu/x86. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve, verified core PRMRR MSRs get programmed only on primary thread avoiding exeception. Change-Id: Ic9648351fadf912164a39206788859baf3e5c173 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18366 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-16soc/intel/skylake: Add support for SPI deviceFurquan Shaikh
Add a new PCI driver for SPI devices with supported PCI ids. Also, provide a translation table to convert struct device structure into SPI bus number. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: If860eb819f2ce5ae5443f808b356af57f86c52be Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18341 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-16soc/intel/skylake: Add GSPI controller get_config supportFurquan Shaikh
Provide implementation of get_config routine for GSPI controller on skylake platforms. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully. Change-Id: I5170076c15d72a7f29acd0989acef5b9149e2ba0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18338 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-16soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL ↵Sooi, Li Cheng
HALO SOC Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC Change-Id: I6a44d55d1588d2620bd1179ea7dc327922f49fd7 Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com> Reviewed-on: https://review.coreboot.org/18028 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-14soc/intel/skylake: Perform CPU MP Init before FSP-S InitSubrata Banik
As per BWG, CPU MP Init (loading ucode) should be done prior to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry (before FSP-S call). BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Boot to OS with all threads enabled. Change-Id: Ia6f83d466fb27e1290da84abe7832dc814b5273a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18287 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-14Revert: soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1Duncan Laurie
This reverts commit 32997fb0bcb9f4183789331a91fd83138776b96f. This change is breaking I2S audio on Kabylake platforms so revert the change to fix audio. BUG=chrome-os-partner:61548,chrome-os-partner:61009 TEST=manual testing on Eve P1 system Change-Id: I3212c8be83078ed57e38501386605e67b87d5bd0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18360 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-14intel/skylake: Disable FADT.8042 if NO_FADT_8042 is setJenny TC
Kernel relies on FADT 8042 flag to enable/disable 8042 interface. If FADT reports 8042 capability and 8042 (/PS2) capability is actually disabled by coreboot, kernel would assume the presence of 8042 based on the FADT flag. This results in undesired system power off when kernel tries to access the 8042 memory region. To address this, CONFIG_NO_FADT_8042 was added to selectively disable 8042 on FADT. BUG=chrome-os-partner:61858 TEST=Boot OS and verify FADT 8042 flag Change-Id: Ic80b3835cb5cccdde1203e24a58e28746b0196fc Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/18307 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-01-22soc/intel/skylake: Include I2C code in romstageDuncan Laurie
The lpss_i2c driver is enabled in romstage, so the SOC needs to export the pre-ram compatible I2C controller info, which for skylake is in the bootblock/i2c.c file. This was not causing a compiler error in normal use, but when adding I2C debug code in romstage it failed to compile. With this added, I can now do I2C transactions in romstage. Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-20soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1Barnali Sarkar
As per Audio PCH team recommendation the iDisplay Audio/SDIN2 should be disabled to bypass InitializeDisplayAudio() function call. Display Audio Codec is HDA-Link Codec, which is not supported in I2S mode BUG=chrome-os-partner:61548 BRANCH=none TEST=Tested to verify that InitializeDisplayAudio() does not get called. Change-Id: Ie0771a8653821e737d10e876313917b4b7c64499 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18091 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-19driver/intel/fsp1_1: Fix boot failure for non-verstage caseTeo Boon Tiong
Currently car_stage_entry is defined only in romstage_after_verstage and as a result when SEPARATE_VERSTAGE is not selected, there is no entry point into romstage and romstage will not be started at all. The solution is move out romstage_after_verstage.S from fsp1.1 driver to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the build and boot issue with this change. Besides that, rename the romstage_after_verstage to romstage_c_entry in more appropriate naming convention after this fix. Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0), romstage can be started successfully. Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/17976 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-19soc/intel/skylake: Add SATA interrupt for APIC modeSooi, Li Cheng
Add SATA interrupt for APIC mode Change-Id: I9e0682e235715399da2c585174925c89b9116ab3 Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com> Reviewed-on: https://review.coreboot.org/18130 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)