| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-04-25 | soc/intel/skylake: use postcar stage for fsp 2.0 | Aaron Durbin |
| 2017-03-28 | soc/intel/common/block: Add cache as ram init and teardown code | Subrata Banik |
| 2017-01-13 | soc/intel/skylake: Rename car_stage.S for fsp2_0 | Teo Boon Tiong |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |