| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-03-08 | x86 chipsets: utilize x86_setup_mtrrs_with_detect() | Aaron Durbin |
| 2016-03-01 | Skylake: Support Intel Speed Shift Technology based on config | Subrata Banik |
| 2016-01-22 | intel/skylake: Thermal Design Power PL1 and PL2 Config Changes | pchandri |
| 2015-11-05 | skylake: Set Pkg Power clamping bit in Power Limit MSR | Rizwan Qureshi |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-10-15 | cpu/mtrr.h: Fix macro names for MTRR registers | Alexandru Gagniuc |
| 2015-10-11 | Skylake: remove the out-dated VR config and un-needed 24mhz calibration | robbie zhang |
| 2015-08-27 | skylake: only generate ACPI cpu entries once | Aaron Durbin |
| 2015-07-29 | skylake: Update microcode reload in ramstage. | Rizwan Qureshi |
| 2015-07-16 | soc/intel: Add Skylake SOC support | Lee Leahy |
| 2015-07-16 | soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC | Lee Leahy |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |