Age | Commit message (Expand) | Author |
---|---|---|
2016-11-21 | fsp2_0: implement stage cache for silicon init | Brandon Breitenstein |
2016-11-11 | soc/intel/skylake: move i2c voltage config to own variable | Aaron Durbin |
2016-09-19 | soc/intel/skylake: Add FSP 2.0 support in ramstage | Naresh G Solanki |
2016-08-31 | skylake: Add initial FSP2.0 support | Rizwan Qureshi |