index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
User &
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
soc
/
intel
/
skylake
/
chip.h
Age
Commit message (
Expand
)
Author
2016-03-01
Skylake: Support Intel Speed Shift Technology based on config
Subrata Banik
2016-02-04
intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown
Archana Patni
2016-01-22
intel/skylake: Thermal Design Power PL1 and PL2 Config Changes
pchandri
2016-01-19
intel/skylake: Adding provision to set voltages to the I2C ports
Naresh G Solanki
2016-01-18
intel/skylake: Change in UPD name from SkipMpInit to FspSkipMpInit
Barnali Sarkar
2016-01-18
intel/skylake: Remove unused devicetree configuration variables
Duncan Laurie
2016-01-18
intel/skylake: Add devicetree setting for DDR frequency limit UPD
Duncan Laurie
2016-01-17
intel/skylake: disable heci1 if psf is unlocked
Archana Patni
2016-01-16
intel/skylake: Add VrConfig UPD parameters from coreboot
Rizwan Qureshi
2016-01-16
intel/skylake: Enable SkipMpInit token
Rizwan Qureshi
2016-01-15
intel/skylake: More UPD params are added for PCH policy in FSP
Rizwan Qureshi
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-27
intel/skylake: Clean up USB configuration in devicetree
Duncan Laurie
2015-10-27
intel/skylake: IRQ programming through UPD
Subrata Banik
2015-10-27
intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params update
Rizwan Qureshi
2015-09-17
intel/skylake: Create "RtcLock" Silicon UPD from coreboot
Barnali Sarkar
2015-09-10
skylake: Enable DPTF based on devicetree setting
Duncan Laurie
2015-09-08
skylake: Clean up chip.h
Duncan Laurie
2015-08-19
skylake: Update Memory and Silicon Init params
Rizwan Qureshi
2015-08-14
skylake: remove ec_smi_gpio and alt_gp_smi_en
Aaron Durbin
2015-08-14
skylake: provide GPE0 routing devicetree configuration
Aaron Durbin
2015-08-14
skylake: remove IedSize from chip.h
Aaron Durbin
2015-08-13
skylake: Add Deep Sx configuration for wake pins
Duncan Laurie
2015-07-21
skylake: Show SPI controller if enabled in devicetree.cb
Duncan Laurie
2015-07-16
soc/intel: Add Skylake SOC support
Lee Leahy
2015-07-16
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC
Lee Leahy