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Age
Commit message (
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Author
2017-11-15
soc/intel/skylake: Make use of common CSE code for skylake
Subrata Banik
2017-10-05
soc/intel/skylake: Add support in SKL for PMC common code
Shaunak Saha
2017-10-03
soc/intel/skylake: Enable common LPC IP
Ravi Sarawadi
2017-07-11
soc/intel/skylake: Fix PMC address range setup for PCH-H
Nico Huber
2017-07-11
soc/intel/skylake: Set generic I/O decode ranges early
Nico Huber
2017-05-09
soc/intel/skylake: Use intel/common/block/smbus code
Aamir Bohra
2017-05-02
soc/intel/skylake: Clean up code by using common FAST_SPI module
Barnali Sarkar
2017-04-28
soc/intel/skylake: Use ITSS common code
Bora Guvendik
2017-04-10
soc/intel/skylake: Use RTC common code
Subrata Banik
2017-04-10
soc/intel/skylake: Use common PCR module
Subrata Banik
2017-03-28
soc/pci_devs.h: Use consistent naming in soc/pci_devs.h
Subrata Banik
2017-03-17
soc/intel/skylake: Fix remaining issues detected by checkpatch
Lee Leahy
2017-03-17
soc/intel/skylake: Wrap lines at 80 columns
Lee Leahy
2016-11-30
soc/skylake: Move IO decode range out from pch_lpc_init
Teo Boon Tiong
2016-10-27
skylake: Prepare GPE for use in bootblock
Duncan Laurie
2016-10-16
soc/intel/skylake: Enable HECI BAR for ME communication
Subrata Banik
2016-08-18
soc/intel/skylake: Move bootblock specific code from skylake/romstage
Naresh G Solanki
2016-08-18
skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init
Rizwan Qureshi
2016-07-28
soc/intel/skylake: Add C entry bootblock support
Subrata Banik
2016-02-04
intel/skylake: unconditionally set SPI controller BAR
Aaron Durbin
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-07-16
soc/intel: Add Skylake SOC support
Lee Leahy
2015-07-16
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC
Lee Leahy