coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-03-17	soc/intel/skylake: Fix remaining issues detected by checkpatch	Lee Leahy
2017-03-17	soc/intel/skylake: Wrap lines at 80 columns	Lee Leahy
2016-11-30	soc/skylake: Move IO decode range out from pch_lpc_init	Teo Boon Tiong
2016-10-27	skylake: Prepare GPE for use in bootblock	Duncan Laurie
2016-10-16	soc/intel/skylake: Enable HECI BAR for ME communication	Subrata Banik
2016-08-18	soc/intel/skylake: Move bootblock specific code from skylake/romstage	Naresh G Solanki
2016-08-18	skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init	Rizwan Qureshi
2016-07-28	soc/intel/skylake: Add C entry bootblock support	Subrata Banik
2016-02-04	intel/skylake: unconditionally set SPI controller BAR	Aaron Durbin
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-07-16	soc/intel: Add Skylake SOC support	Lee Leahy
2015-07-16	soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC	Lee Leahy