| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-03-28 | soc/intel/common/block: Add cache as ram init and teardown code | Subrata Banik |
| 2017-03-24 | soc/intel/skylake: Use C entry code for MTRR programming | Subrata Banik |
| 2017-03-17 | soc/intel/skylake: Wrap lines at 80 columns | Lee Leahy |
| 2016-08-18 | soc/intel/skylake: Correct Cache as ram size | Rizwan Qureshi |
| 2016-07-28 | soc/intel/skylake: Do cache as ram and prepare for C entry | Subrata Banik |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |