coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-03-30	soc/intel/skylake: Save/restore GMA OpRegion address	Matt DeVillier
2017-10-20	soc/intel/skylake: Add GNVS variables and include SGX ASL	Pratik Prajapati
2017-08-10	soc/intel/skylake: Enable UART debug controller on S3 resume	Furquan Shaikh
2017-06-07	src: change coreboot to lowercase	Martin Roth
2016-10-26	intel/skylake: Add support to enable wake-on-usb attach/detach	Furquan Shaikh
2016-03-08	skylake: Add and fill out CID1 NVS field	Duncan Laurie
2015-12-03	intel/skylake: Add ACPI device for audio controller	Duncan Laurie
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-14	skylake: ACPI: Fix compiler warnings with iasl-20150717	Duncan Laurie
2015-09-09	intel/skylake: ACPI: Clean up formatting in and fix ASL code	Duncan Laurie
2015-09-08	skylake: ACPI: Remove SerialIO ACPI mode code	Duncan Laurie
2015-09-08	skylake: ACPI: Fix and clean up PCIE _PRT entries	Duncan Laurie
2015-08-29	intel/skylake: Add support for DPTF	Shilpa Sreeramalu
2015-08-14	skylake: fix invalid GNVS base address	Aaron Durbin
2015-07-16	soc/intel: Add Skylake SOC support	Lee Leahy
2015-07-16	soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC	Lee Leahy