coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-05-18	soc/intel: Add support for USB ACPI code generation	Duncan Laurie
2018-04-24	compiler.h: add __weak macro	Aaron Durbin
2018-04-20	pci: Move inline PCI functions to pci_ops.h	Patrick Rudolph
2018-04-05	soc/intel/skylake: Generate ACPI DMAR table	Nico Huber
2018-03-06	soc/intel/skylake: Remove MCFG constants	Duncan Laurie
2018-03-06	soc/intel: Fix MCFG end bus number	Duncan Laurie
2018-02-22	soc/intel/skylake: Do not set ACPI_FADT_LEGACY_DEVICES	Furquan Shaikh
2018-01-31	soc/intel/skylake: Always add PM1_TMR block to FADT	Duncan Laurie
2017-11-15	soc/intel: Enable ACPI DBG2 table generation	Duncan Laurie
2017-10-20	soc/intel/skylake: update GNVS with SGX data	Pratik Prajapati
2017-10-03	soc/intel/skylake: Enable common LPC IP	Ravi Sarawadi
2017-09-14	device: acpi_name() should take a const struct device	Aaron Durbin
2017-06-09	soc/intel/skylake: Use CPU common library code	Barnali Sarkar
2017-06-05	soc/intel/skylake: Add config for cpu base clock frequency	Aamir Bohra
2017-05-25	soc/intel/skylake: Implement GPIO ACPI AML generating functions	Furquan Shaikh
2017-05-16	soc/intel/skylake: Add option to enable/disable EIST	Subrata Banik
2017-04-28	intel/skylake: Switch FADT to ACPI version 3.0	Werner Zeh
2017-04-13	soc/intel/skylake: Split AC/DC settings for Deep Sx config	Duncan Laurie
2017-03-28	soc/pci_devs.h: Use consistent naming in soc/pci_devs.h	Subrata Banik
2017-03-17	soc/intel/skylake: Fix remaining issues detected by checkpatch	Lee Leahy
2017-02-19	soc/intel/skylake: Disable s0ix if not enabled in devicetree	Duncan Laurie
2017-02-14	intel/skylake: Disable FADT.8042 if NO_FADT_8042 is set	Jenny TC
2016-10-28	soc/intel/skylake: don't hardcode GPE0 standard reg	Aaron Durbin
2016-10-27	skylake: Fix wake source reporting with Deep S3	Duncan Laurie
2016-10-27	skylake: Use COMMON_FADT	Duncan Laurie
2016-10-26	intel/skylake: Add support to enable wake-on-usb attach/detach	Furquan Shaikh
2016-09-19	soc/intel/skylake: Add FSP 2.0 support in ramstage	Naresh G Solanki
2016-03-08	skylake: Add and fill out CID1 NVS field	Duncan Laurie
2016-02-04	intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown	Archana Patni
2016-01-19	intel/skylake: Fix issues found by klockwork	Naresh G Solanki
2015-12-15	x86 acpi: remove ALIGN_CURRENT macro	Aaron Durbin
2015-12-03	intel/skylake: Remove unused code to add SSDT2	Duncan Laurie
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-27	intel/skylake: Add support for Gfx PEIM (AKA GOP)	robbie zhang
2015-09-17	skylake: Use common ACPI _SWS code	Duncan Laurie
2015-09-17	Skylake: update C state latency and power numbers	robbie zhang
2015-09-10	skylake: Move ACPI init to SOC instead of mainboard	Duncan Laurie
2015-09-10	skylake: Enable DPTF based on devicetree setting	Duncan Laurie
2015-08-14	skylake: provide clarification for FADT gpe0_blk_len	Aaron Durbin
2015-07-16	soc/intel: Add Skylake SOC support	Lee Leahy
2015-07-16	soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC	Lee Leahy