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2022-10-20soc/intel/meteorlake: Add support to skip the MBP HOBWonkyu Kim
This patch adds the support to enable/disable skipping MBP HOB from the devicetree based on mainboard requirement. Porting the feature from commit 2bc54e7c001c ("soc/intel/alderlake: Add support to skip the MBP HOB") TEST=Build and boot to verify that the right value has been passed to the FSP. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I360d33617b9d2626fce5600e861214b0747f57b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-12soc/intel: Kconfig: Correct UART source clock value in commentWonkyu Kim
Correct UART source clock value in comment from 120 MHz to 100 MHz. BUG=b:249530903 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ifc17357051ae0b3bc663da467b4fc809a46024d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68286 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7ddb4ea792b9a2153b7c77d2978d9e1c4544535d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-06soc/intel/meteorlake: Make use of is_devfn_enabled() functionSridhar Siricilla
The patch uses is_devfn_enabled() function to enable the TBT PCIe ports through FSP-M and FSP-S UPDs. Also, removes unused tbt_pcie_port_disable array member from soc_intel_meteorlake_config struct. TEST=Build coreboot for Google/Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ie55e196bd8f682864b8f74dbe253f345d7184753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-27acpi/acpi_pm.c: refactor acpi_pm_state_for_* functionsFabio Aiuto
Use just one function to get the chipset powerstate and add an argument to specify the powerstate claimer {RTC,ELOG,WAKE} and adjust the failure log accordingly. TEST: compile tested and qemu emulation successfully run Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I8addc0b05f9e360afc52091c4bb731341d7213cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/67618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-22soc/intel/spi: Move BIOS flash SPI controllers to fast SPI driverWerner Zeh
There are two classes of SPI controllers on Intel chipsets: * generic usable SPI controllers * SPI controller hosting the BIOS flash (fast SPI controller) While the first class can be used for generic peripheral attachment the second class mostly controls the BIOS flash and a TPM device (if enabled). The generic SPI driver is not fully applicable to the fast SPI controller. In addition, the fast SPI controller reports the reserved MMIO range used for the BIOS flash mapping so that the OS is aware of this range. This patch moves the fast SPI controller of all known SoCs to the fast SPI driver in common code. In addition, the PCI device for the fast SPI controller is removed from the function 'spi_soc_devfn_to_bus' as this is a callback of the generic SPI driver. Change-Id: Ia881c1d274acdcf7f042dd8284048a7dd018a84b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-21soc/intel/meteorlake: Skip the TCSS D3 cold entry sequencezhaojohn
This patch provides a workaround which skips requesting IOM for D3 cold entry sequence. BUG=b:244082753 TEST=Verified MUX configuration after hot plugging Type-C devices on Rex and MTL RVP boards. Change-Id: I17bcde75360c4b2b40885d355702e3e5f45d770a Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-16soc/intel/meteorlake: Enable `SOC_INTEL_COMMON_BLOCK_CNVI` configSubrata Banik
TEST=Able to build and boot Google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I64aab8391f89414754785cea47671f3350324297 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-15soc/intel/meteorlake: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia2508abe62a194f2921d5535937ba82a60967ca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-14soc/intel/mtl: Fix GPIO group pad base for ACPIKapil Porwal
This patch fixes MeteorLake GPIO PINCTRL entries as per 5.15 kernel pintrl driver: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.15/drivers/pinctrl/intel/pinctrl-meteorlake.c In order to support using ACPI GPIOs it is necessary for coreboot to be compatible with this implementation. The GPIO groups that are usable by the OS are declared with a pad base which is then used to compute the number for ACPI GPIOs. BUG=b:232573696 TEST=Tested on Google Rex board. After this change, driver rt5682s is able to claim pinctrl IRQ 358 corresponding to GPP_B06. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Icabbe9e125ee9efaf0eef4c4cdc8be9f734aa703 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67565 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-14soc/intel/meteorlake/retimer: Change loglevel prefixIvy Jian
This message is not really an error message, so BIOS_ERR is inappropriate. Since the message is informational, switch to BIOS_INFO instead. BUG=b:244687646 TEST=emerge-rex coreboot before [ERROR] USB Type-C 0 mapped to EC port 0 after [INFO] USB Type-C 0 mapped to EC port 0 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ia08fd45dd484c79d81527ea46cfaaa5a01a410c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67536 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-14soc/intel/meteorlake: Enable TcssDma1EnIvy Jian
Adding support enables/disables TcssDma1En by usb4_params. BUG=b:244687646 TEST= TcssDma1En is enabled as expected. before patch [SPEW ] PCI: 00:0d.2 [8086/0000] bus ops [DEBUG] PCI: 00:0d.2 [8086/7ec2] enabled [INFO ] PCI: Static device PCI: 00:0d.3 not found, disabling it. after patch [SPEW ] PCI: 00:0d.2 [8086/0000] bus ops [DEBUG] PCI: 00:0d.2 [8086/7ec2] enabled [SPEW ] PCI: 00:0d.3 [8086/0000] bus ops [DEBUG] PCI: 00:0d.3 [8086/7ec3] enabled Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I9cd8fc3819f533e9581fea19d4da48283888cc04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67534 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-14soc/intel/meteorlake: Enable tbtPcie2/3Ivy Jian
Adding support enables/disables tbtPcie2/3 by usb4_params. BUG=b:244687646 TEST= TRP2/3 are enabled as expected. before patch [INFO ] PCI: Static device PCI: 00:07.2 not found, disabling it. [INFO ] PCI: Static device PCI: 00:07.3 not found, disabling it. after patch [DEBUG] PCI: 00:07.2 subordinate bus PCI Express [DEBUG] PCI: 00:07.2 [8086/7ec6] enabled [DEBUG] PCI: 00:07.3 subordinate bus PCI Express [DEBUG] PCI: 00:07.3 [8086/7ec7] enabled Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ia1bdc9b5c0533bdddae67b8039103162a57fdc39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67530 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-12src/soc/intel/mtl: Remove Storage UPDSrinidhi N Kaushik
This change removes all references to HybridStorageMode UPD since it has been deprecated starting from FSP v2344_00 BUG=b:245167089 TEST=build coreboot mtlrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I16eb33cb1260484b0651d40211323c6ae986a546 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-10soc/intel/meteorlake: Hook up common code for thermal configurationSubrata Banik
Thermal configuration registers are now located behind PMC PWRMBASE for MeteorLake as well (same as ADL). Hence, using thermal common code to sets the thermal low threshold as per mainboard provided `pch_thermal_trip`. Note: These thermal configuration registers are RW/O hence, setting those early prior to FSP-S helps coreboot to set the desired low thermal threshold for the platform. TEST=Dump thermal configuration registers PWRMBASE+0x150c etc on Google/rex prior to FSP-S shows that registers are now programmed based on 'pch_thermal_trip' and lock register BIT31 is set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1d6b179a1ed43f00416d90490e0a91710648655e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67462 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-10soc/intel/meteorlake: Update `pch_thermal_trip` for MTLSubrata Banik
This patch updates `pch_thermal_trip` as per Intel MTL vol1 chapter 14. Additionally, dropped the `FIXME` tag for `pch_thermal_trip`. TEST=Able to boot the Google/rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I86f97c9245fe953832d3b408aa902d6a41e55651 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67461 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-10soc/intel/meteorlake: Drop redundant `MCHBAR` programming in romstageSubrata Banik
This patch drops redundant MCHBAR programming in romstage as bootblock already done with MCHBAR setting up. TEST=Able to boot Google/Rex to ChromeOS and MCHBAR is set to correct value as per iomap.h Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic2c05f47ab22dc7fe087782a1ce9b7b692ea157e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-10soc/intel/meteorlake: Disable FSP UPDs related to virtualizationSubrata Banik
This patch disables FSP UPDs (`VtdDisable` and `VmxEnable`) as kernel cmdline still passes `intel_iommu=off` to turn off virtualization. BUG=b:241746156 TEST=Able to boot Google/rex to ChromeOS UI. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I21e178a93e311889f2ab7d1a08230d21b051f45e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67452 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-08soc/intel/meteorlake: Hook up PAVP to KconfigSubrata Banik
Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. TEST=Able to boot Google/rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I416346995d744990054c8e0c839ada82c84b7550 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67423 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/intel/meteorlake: Update MTL_USE_COREBOOT_MP_INIT descriptionSridhar Siricilla
The patch update MTL_USE_COREBOOT_MP_INIT Kconfig description. TEST=Build code for MTL Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I38609cb03714084dd9092f41dd6e5b418a7f120a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-26soc/intel/mtl: Activate TME on all CPUsTarun Tuli
This patch runs `set_tme_core_activate()` on all CPUs (BSP+APs) as per MTL processor EDS. TEST= Able to build and boot RVP. Confirmed TME supported mode detected via temporary debug prints and MSR 0x9ff indicates activated. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Id368925504d81025239e94698d2cb0e2266a5a96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66949 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSSJohn Zhao
This change provides access to IOE through P2SB Sideband interface for Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication. There is a policy of locking the P2SB access at the end of platform initialization. The tbt_authentication is read from IOM register through IOE P2SB at early silicon initialization phase and its usage is deferred to usb4 driver. BUG=b:213574324 TEST=Built coreboot and validated booting to OS successfully on MTLRVP board. No boot hung was observed. Signed-off-by: John Zhao <john.zhao@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8dcee90080c6e70dadc011cc1dbef3659fdbc8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66951 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25soc/intel/mtl: Hook up Lp5CccConfig FSP UPDKapil Porwal
Hook up Lp5CccConfig FSP UPD for Intel MeteorLake. BUG=b:243734885 TEST=Built and booted on Google Rex. Verified the UPD value in MRC log. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3d7ff8e08546f06cf7807ee825cfef84c14a6c5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67052 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Hook up ECT FSP UPDKapil Porwal
Hook up ECT FSP UPD for Intel MeteorLake. BUG=b:243734885 TEST=Built and booted on Google Rex. Verified the UPD value in MRC log. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Idc23717c3ce52e3635e2da41733058f912545e5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67051 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Program MCHBASE prior enabling extended bios rangeSubrata Banik
This patch resolves the SoC programming dependency order where enabling extended bios support requires MCHBASE to be enabled. BUG=b:243693375 TEST=Able to boot from RW-A slot which is mapped to extended BIOS range. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8bd9c3d3fb5e82e34f2d6af8548452c744d4b3c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67046 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24soc/intel/meteorlake: Enable GPIO 4 bits pad mode configurationJamie Ryu
This enables SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS to support 4 bits GPIO pad mode to configure native function 8 to 15. BUG=b:239690757 TEST=build and verify pad mode configuration with Meteor Lake mtlrvp Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ibf4b13a3d19095d15bf857c7fe4ec0affb54a4e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66391 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-21soc/intel: Enable TME based on supported CPU SKU and config optionSubrata Banik
This patch removes the static kconfig being used to fill in TME enable FSP UPD. Instead use`is_tme_supported()` and `CONFIG(INTEL_TME)` to check if the CPU has required TME support rather than hardcoding. TEST=FSP debug log shows `TmeEnable` UPD is set appropriately for the TME-supported CPU SKUs. As per FSP-M debug log: Without this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x1 With this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8aa2922baaf2a49e6e2762d31eaffa7bdcd43b0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66750 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21soc/intel: Unravel `INTEL_TME` Kconfig optionAngel Pons
The `INTEL_TME` Kconfig option has a prompt, which means it is meant to be user-configurable. However, it has been selected from Alder Lake and Meteor Lake Kconfig, so `INTEL_TME` cannot be disabled on them. Replace the `select INTEL_TME` statements with default values in order for this option to be user-configurable on all platforms that support it. Change-Id: Ib37c108fcc1004840b82be18fd23c340a68ca748 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66756 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-18Revert "soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSS"Subrata Banik
This reverts commit eb80b1efa36c99e485b2604e913c2aa316168eea. Reason for revert: Results into hard hang with serial debug msg inside FSP-S. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8e7cf804828da8939f591eb0770c8daf830c8d94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-12soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSSJohn Zhao
This change provides access to IOE through P2SB Sideband interface for Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication. There is a policy of locking the P2SB access at the end of platform initialization. The tbt_authentication is read from IOM register through IOE P2SB at early silicon initialization phase and its usage is deferred to usb4 driver. BUG=b:213574324 TEST=Built coreboot and validated booting to OS successfully on MTLRVP board. No boot hung was observed. Change-Id: Icd644c945bd293a8b9c4a364aaed99ec4a7c12f9 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-12soc/intel/meteorlake: Have non prefetchable MMIO for IGD BAR0Wonkyu Kim
Enable SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO for MTL to fix guc driver failure. BUG=b:241746156 TEST=boot to OS and check guc driver loading successful Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ifc20935bccdda55db3e57eecd37a4260b3f1a2d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66613 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11src/soc/intel/mtl: Add VPU supportSrinidhi N Kaushik
This change adds support for enabling VPU on MTL SoC. BUG=b:240665069 TEST=build coreboot mtlrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie79b45f34a669b9ff777599cb85217abac6cb74e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2022-08-05soc/intel/mtl: Remove deprecated FSP optionSrinidhi N Kaushik
Remove the reference to `CpuCrashLogDevice` UPD since FSP v2304.01 has deprecated this UPD. BUG=b:240665069 TEST=build rex coreboot Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I23223fd7936a60d974229b553de255a7dcf4416b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66357 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-28soc/intel/meteorlake: Fix GPIO reset mapping as per GPIO BWGSubrata Banik
This patch fixes the documentation discrepancy of GPIO reset type between PCH EDS and GPIO BWG. As per GPIO BWG, there are four GPIO reset types in Meteor Lake as below: - Power Good - (Value 00) - Deep - (Value 01) - Host Reset/PLTRST - (Value 10) - Global Reset for GPP - (Value 11) Also, dropped the need for having dedicated reset type for GPIO community 3. As per the MTL EDS, all GPIO communities have the same reset type. BUG=b:213293047 TEST=Able to build and boot Google/Rex without below error msg. [ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id7ea16d89b6f01b00a7b7c52945f6e01e8db6cbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/66155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Will Kim <norwayforest92@gmail.com>
2022-07-27soc/intel/meteorlake: Use coreboot native event handler for FSP-SSrinidhi N Kaushik
Beginning FSP 2.2 specifications Fsps Config Upd "FspEventHandler" was moved to Fsps Arch Upd. Hence we were not seeing Fsps Debug log was not using coreboot debug library. This change assigns Fspd Arch Upd FspEventHandler with coreboot ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig is enabled. Before: Dumping FSPS_UPD - Size: 0x00001510 0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02 0x00 0x00 0x00000010: 0x00 With the fix: [SPEW ] Dumping FSPS_UPD - Size: 0x00001528 [SPEW ] 0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02 [SPEW ] 0x00000010: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 [SPEW ] 0x00000020: 0x01 0x00 0x00 0x00 0x20 0x00 0x00 0x00 0xAA [SPEW ] 0x00000030: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 [SPEW ] 0x00000040: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 BUG=b:237263080 TEST=Able to build and boot MTL RVP, verified the FSP-S debug log is using coreboot debug library. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie63258f6427b3da7927a866bc3767f548b16e3e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-25Revert "soc/intel/meteorlake: Align TCSS functions through SBI"Subrata Banik
This reverts commit b57d172fbb5265d632c031532fcc2aec156e065a. Reason for revert: Results into hard hang with serial debug msg as below: `[EMERG] Unable to unhide the P2SB device!` Intel team is working towards to fix this issue. BUG=b:239806774 TEST=Able to boot the Intel/MTLRVP with this revert. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic6be37c000afdf4f0c6c22497c233aa0bbc49d48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65500 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-25soc/intel/meteorlake: Choose PCR write to lock GPIO PADSubrata Banik
Set the SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR config on Meteor Lake to instruct Pad Configuration Lock. BUG=b:211573253, b:211950520, b:213596994 TEST=Able to perform GPIO lock programming without error on MTLRVP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icd123adb02716149fa51c9e4c987c281f9de2f43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-25soc/intel/meteorlake: Debug consent is set to 3 (USB3 DbC)Subrata Banik
This patch ensures the debug consent value is matching with the inline comment. TEST=Able to build the Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icf72eb2aa4064fd78f4f99570a4cf44e41932ec3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66008 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20soc/intel/common/pch: Decouple CLIENT from BASEAngel Pons
In preparation to add a third option, have "Client" platforms select a dedicated Kconfig option instead of the common "_BASE" option. Rewrite the help texts to clarify what "Client" and "Server" mean, because the terms refer to the type of silicon and not to the market segment. Some uniprocessor (single-socket) servers are actually client platforms and there are some multi-socket workstations based on a server platform. Change-Id: I646729d709f60ca2b5e74df18c2b4e52f9b10e6b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-18soc/intel/meteorlake: Allow possible options for MP InitSubrata Banik
Ported back from commit ceaf9d116949da68aa9c ("soc/intel/alderlake: Allow possible options for MP Init") This patch creates choice that lists all possible options to perform MP Init as below for Intel Meteor Lake platform: 1. MTL_USE_FSP_MP_INIT: Allow coreboot to bring APs from reset and FSP runs feature programming based and selects MP_SERVICES_PPI_V2 config. 2. MTL_USE_COREBOOT_MP_INIT: Allow coreboot to perform MP Init (both AP init and feature programming) using native implementation. Additionally, selects required RELOAD_MICROCODE_PATCH when coreboot is expected to run MP Init. Refactor SoC code to allow required FSP UPD override based on selected MP Init option. Additionally, added `FIXME` comment to ensure Intel MTL FSP can bring back SkipMpInit UPD in MTL to let coreboot override this UPD and ensure independent MP Init flow. BUG=b:219053812 TEST=Able to build google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic917e4e03e24d73190cfc72c6ed8e59af427bedf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65743 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18soc/intel/meteorlake: Choose coreboot doing MP Init over FSPSubrata Banik
This patch enables coreboot doing Multiprocessor Initialization (MP) for Meteor Lake CPU using the native coreboot drivers and passes the MP PPI data structure to let FSP to perform CPU feature programming (anything that is restricted) as part of FSP-S. Additionally, modify the kconfig inclusion order alphabetically. BUG=b:219061518, b:219053812 TEST=Able to bring all APs from reset by coreboot and successfully able to perform all CPU feature programming using MP PPI services. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic2781ee0b39e42aa579b72d3d4ee6586d5a89a02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65742 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18soc/intel/meteorlake: Enable `DEFAULT_X2APIC_LATE_WORKAROUND`Subrata Banik
This patch ensures Intel Meteor Lake can enable the X2APIC feature. While debugging Intel Meteor Lake (MTL) based platforms it seems like enabling `DEFAULT_X2APIC` runs into a hang while coreboot tries to bring the application processors (APs) from reset using X2APIC mode. [INFO ] LAPIC 0x10 switched to X2APIC mode. ... [DEBUG] Attempting to start 3 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [ERROR] Not all APs checked in: 0/3. [DEBUG] 0/3 eventually checked in? [ERROR] MP initialization failure. [ERROR] MP initialization failure. Note: The AP bring up flow between XAPIC and X2APIC are the same except the way to access those LAPIC registers. X2APIC expects to access all LAPIC registers using MSR (base with 0x800). The correct flow to enable X2APIC on MTL would be as follows: 1. Let BSP bring all APs in XAPIC mode. [INFO ] LAPIC 0x10 in XAPIC mode. ... [DEBUG] Attempting to start 3 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [INFO ] LAPIC 0x11 in XAPIC mode. [INFO ] LAPIC 0x0 in XAPIC mode. [INFO ] LAPIC 0x80 in XAPIC mode. 2. Call enable_x2apic() function on all CPUs (BSP and APs) And at the end of #2 above, all cores will now switch to X2APIC from XAPIC. [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor Intel device a06a0 [DEBUG] Clearing out pending MCEs [INFO ] LAPIC 0x10 switched to X2APIC mode. ... [INFO ] CPU #0 initialized [INFO ] Initializing CPU #1 [DEBUG] CPU: vendor Intel device a06a0 [DEBUG] Clearing out pending MCEs [INFO ] LAPIC 0x11 switched to X2APIC mode. Note: Intel MTL FSP also follow the same steps for x2APIC enablement while coreboot selects USE_INTEL_FSP_MP_INIT config instead MP_SERVICES_PPI_V2. BUG=b:219061518, b:219053812 TEST=Able to perform coreboot doing AP init with DEFAULT_X2APIC_LATE_WORKAROUND config enabled without running into any hang issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie9c8fad6c46b15b5b08c9cc4ef53f2a6872bd0ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65741 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18soc/intel/meteorlake: Account for GSPI2 everywhereAngel Pons
Commit e54a8fd43247d767f16a37f3e3150b2915d809bc (soc/intel/meteorlake: Add entry for GSPI2 device) added an entry for the GSPI2 device in the devicetree, but did not add any other entries. Ensure that the rest of the code is aware of the GSPI2 device to avoid any problems. Change-Id: Ib59bd289751bd96402c4adc61ffbee3bebe0edb0 Found-by: Coverity CID 1490681 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-07-14soc/intel/meteorlake: Add entry for GSPI2 deviceSubrata Banik
This patch adds GSPI2 (PCI device B0:D18:F6) entry into the chipset.cb. Additionally, increases `CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX` value to include GSPI2 as well. BUG=b:224325352 TEST=Able to build and boot Google/Rex platform. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I901128a1773fc6d2ba87e3e4972f45ad4a754d35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65675 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13soc/intel/meteorlake: Use double digit GPIO pad numbersKapil Porwal
Google uses two digit GPIO pad numbers for internal GPIO references and Intel has updated their GPIO naming schemes too (see the GPIO implementation worksheet #641238) so use double digit GPIO pad numbers. Format - "GPP_%c%02d", gpio_group, gpio_pad_num e.g. GPP_A0 -> GPP_A00, GPP_V2 -> GPP_V02, GPP_C9 -> GPP_C09 etc. BUG=b:238196741 TEST=Able to build meteorlake based google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ieb7569c1a35b08c0970a604ec7b4b91e6179dd28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65719 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-11soc/intel/meteorlake: Align TCSS functions through SBIJohn Zhao
This change aligns the Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication through the sideband access. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I393f6e1c7d322878cbb684cd95bfa2477195b23a Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-07soc/intel/common/graphics: Add another Meteor Lake device IDWonkyu Kim
Add 0x7d55 as another ID for Meteor Lake graphics controllers. TEST=Boot with MTL silicon to check coreboot log for DID2 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iea01f6d4f2469fc0eeac73a3f1c4b9af1f39463c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2022-07-07soc/intel/meteorlake: Remove `ADL` instancesSubrata Banik
This patch removes all instances of the `ADL` from Meteor Lake SoC directory. TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8153b2070467beb582ce1f70be97272ce09ca04c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65667 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07soc/intel/meteorlake: Update IFD_CHIPSET kconfig valueSubrata Banik
This patch updates IFD_CHIPSET kconfig value from `ifd2` to `mtl`. TEST=Able to build and boot Google/Rex image on MTL emulation platform. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I416f881bcbe3dd7494ead636d6b593366a51b31c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-05soc/intel/meteorlake: Enable X2APICSubrata Banik
This patch enables X2APIC to avoid hang-ups due to `Switching from X2APIC to XAPIC mode is not implemented.`  BUG=b:237924211 ([MTL-FSP][v2222.1] Lists of boot issue with MTL FSP) TEST=Able to enable X2APIC on rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I58649a9a6c9c0ba86856f6aa5fb470e2ef774e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65617 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-03soc/intel/meteorlake: Use coreboot native event handler for FSP-M/SSubrata Banik
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig is enabled. BUG=b:237263080 TEST=Able to build and boot MTL simics. Also, verified the FSP debug log is using coreboot debug library as below: Before: Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000F961B000, size is 0x00150000, handle is 0xF961B000 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 With this code change: [SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE [SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 [SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A [SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000 [SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 [SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 [SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I80ba73afed642e6d21c5310e9bf734f6f7170347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-01soc/intel/mtl: Add GPIOs for Meteor Lake SOCRavi Sarawadi
Add definitions for the GPIO pins on Meteor Lake SoC, as well as GPIO IRQ routing information and supporting ACPI ASL. For now, add the following GPIO communities and GPIO groups: Comm. 0: GPP_CPU, GPP_V, GPP_C Comm. 1: GPP_A, GPP_E Comm. 3: GPP_H, GPP_F, SPI0, VGPIO3 Comm. 4: GPP_S, JTAG Comm. 5: GPP_B, GPP_D, VGPIO BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I7fe9654f22b074a9af18eb7bcdc21812dee77035 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64169 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/mtl/acpi: Add SoC ACPI directory for Meteor LakeRavi Sarawadi
List of changes: 1. Select common ACPI Kconfig to include common ACPI code block from IA-common code 2. Select ACPI Kconfig support for wake up from sleep states. 3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH, LAN, HDA etc. BUG=b:224325352 TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Change-Id: Iebe3d38f50e202d75add88f336b5f3e9ba9f5a22 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64168 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/mtl: Do initial Meteor Lake SoC commit till ramstageRavi Sarawadi
List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Fill required FSP-S UPD to call FSP-S API BUG=b:224325352 TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/meteorlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiBSubrata Banik
Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB helps in improving overall boot time since it reduces hashing and body loading time (~30ms). Backport changes from commit hash 84532dae1 (soc/intel/alderlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiB). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3784b99bf06e0c03d123f290a98a0b1e4528b8d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64792 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29soc/intel/mtl: Do initial Meteor Lake SoC commit till romstageRavi Sarawadi
List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API BUG=b:224325352 TEST=Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I3d5c6ceb7f97429ff903e7577186e8d8843c1f14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63363 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-27soc/intel/*/Kconfig: Fix typo in commentAngel Pons
clcok ---> clock Change-Id: Ie41524f6500479162984fa9050d942f4e295f00a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-22soc/intel: Add Meteor Lake SA device IDSubrata Banik
Add Meteor Lake SA device ID 0x7d14 (4+8, 15W). BUG=b:224325352 TEST=Able to build MTL SoC and verified SA DID is now shown proper. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I051a40136ed89e837945bf4569c77d2a80375ed6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65111 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-06soc/intel/meteorlake: Refactor bootblock SoC programming codeSubrata Banik
This patch ensures the IP initialization being done as part of MTL bootblock code is able to complete the bootblock phase without any visible hang. The re-ordering in the MTL bootblock SoC programming is required to ensure the SA early initialization is taking place prior to performing any PCI Read/Write operation (like P2SB bar enabling for IOE die etc.). Additionally, Fast SPI init takes place prior to enabling ROM caching etc. BUG=b:224325352 TEST= Able to build and start booting the MTL simics. Without this change, the code execution is stuck as below: [NOTE ]  coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8) [DEBUG]  CPU: Intel(R) Core(TM) i7 CPU (server)     @ 2.00GHz [DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: 80000018 [DEBUG]  CPU: AES supported, TXT supported, VT supported [DEBUG]  MCH: device id 7d02 (rev 00) is MeteorLake P [DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC [DEBUG]  IGD: device id ffff (rev ff) is Unknown [INFO ]  PMC: Using default GPE route. [INFO ]  VBNV: CMOS invalid, restoring from flash [ERROR]  init_vbnv: failed to locate NVRAM [EMERG]  Cannot locate primary CBFS Able to detect the Flash and reading the SPI flash layout in proper with this change as below: [NOTE ]  coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8) [DEBUG]  CPU: Intel(R) Core(TM) i7 CPU (server)     @ 2.00GHz [DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: 80000018 [DEBUG]  CPU: AES supported, TXT supported, VT supported [DEBUG]  MCH: device id 7d02 (rev 00) is MeteorLake P [DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC␛␛[DEBUG]  IGD: device id ffff (rev ff) is Unknown [INFO ]  PMC: Using default GPE route. [INFO ]  VBNV: CMOS invalid, restoring from flash [DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1804000. [DEBUG]  FMAP: base = 0x0 size = 0x2000000 #areas = 33 [DEBUG]  FMAP: area RW_NVRAM found @ 112b000 (24576 bytes) [INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-06soc/intel/meteorlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KBSubrata Banik
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix cbmem buffer overflow issue. Test=Boot MTL simics and check cbmem -c | grep 'CBFS: Found' lists all stages. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5dc5d5b99003b59b2262bd1e4eb5ccb11d721195 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-06soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblockRavi Sarawadi
Base code is based of Intel Alder Lake SOC code. List of changes: 1. Add required Meteor Lake SoC programming till bootblock 2. Include only required headers into include/soc 3. Include MTL-P related DID, BDF 4. Ref: Processor EDS documents vol1 #621483, vol2 #640858 TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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