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2024-09-19soc/intel/mtl: Hook up GMA ACPI brightness controlsJeremy Soller
Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Change-Id: Ied08e5e9fe4913bd60474ed7dcf88b945172558d Signed-off-by: Jeremy Soller <jeremy@sysetm76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-18soc/intel: Move CSE update ELOG to cse_lite.cSubrata Banik
The ELOG for CSE updates was being added in fsp_params.c, but the actual update happens in cse_lite.c. This commit moves the ELOG to cse_lite.c to more accurately reflect where the event is happening. This also removes the need for a sol_type variable in meteorlake/romstage/fsp_params.c. It also helps to avoid redundant ELOG event entry while performing CSE update (due to CSE RO to RW switch dependency). BUG=b:361253028 (Multiple CSE sync elog prints for Nissa/Trulo) TEST=Able to see only one instance of ELOG while performimg CSE sync. w/o this patch: elogtool list 0 | Log area cleared | 4088 1 | Kernel Event | Clean Shutdown 2 | Early Sign of Life | MRC Early SOL Screen Shown 3 | Early Sign of Life | CSE Sync Early SOL Screen Shown 4 | System boot | 29 5 | Memory Cache Update | Normal | Success 6 | Early Sign of Life | CSE Sync Early SOL Screen Shown w/ this patch: elogtool list 0 | Log area cleared | 4088 1 | Early Sign of Life | MRC Early SOL Screen Shown 2 | Memory Cache Update | Normal | Success 3 | System boot | 30 4 | Memory Cache Update | Normal | Success 5 | Early Sign of Life | CSE Sync Early SOL Screen Shown Change-Id: I37fe3f097e581f79bf67db1ceb923f10ce651d62 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-09-17Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"Subrata Banik
This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309. This workaround is not valid with the latest Intel PRQ silicon, so I'm dropping it now. Additionally, able to boot to ChromeOS without any hang, and I also ran an S0ix cycle without any failures. BUG=b:244082753 TEST=Able to boot google/rex0 to CrOS. Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84368 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-07drivers/intel/fsp2_0: Consolidate `BUILDING_WITH_DEBUG_FSP` optionSubrata Banik
Move the `BUILDING_WITH_DEBUG_FSP` Kconfig option from SoC-specific files to the FSP2_0 driver Kconfig to avoid duplication. Also slightly improves the option's prompt and help text. TEST=Built and booted google/rex successfully. Change-Id: I5c3dce59c396f6c1665a3ed1b8c1bb5df0f5a8d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-07drivers/intel/fsp2_0: Add Kconfig option to control MBP HOB creationSubrata Banik
This patch adds a new Kconfig option `FSP_PUBLISH_MBP_HOB` to control the creation of the ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. Disabling this option can improve boot time on platforms that do not utilize the MBP HOB, such as ChromeOS devices. The option is disabled by default on ChromeOS and enabled by default on other platforms. On ADL-P based platforms, this option is forced to be enabled as ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. Removed SoC specific implementation of `FSP_PUBLISH_MBP_HOB` config from MTL and TGL config file. TEST=Tested on ADL-P and ADL-N platforms. Verified that MBP HOB is created when `FSP_PUBLISH_MBP_HOB` is enabled and not created when it is disabled. Also verified that the system boots successfully in both cases. Change-Id: I21da00259c0b9bcca6f545291a6259e9cce8d900 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-04soc/intel: Refactor ITSS macrosSubrata Banik
This patch refactors ITSS related SoC specific macros by consolidating them into a common itss.h file. This improves code maintainability and reduces redundancy as each SoC previously defined the same macros. Specific changes include: - Move SoC specific ITSS macros into intelblocks/itss.h. - SoC code now includes intelblocks/itss.h instead of the SoC-local soc/itss.h. - Drop soc/itss.h from static ASL files. - Delete soc/itss.h from all SoC locals except Apollo Lake and Sky Lake. TEST=Able to build and boot google/hatch, google/xol and google/karis. Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84183 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-09-04soc/intel: Remove unused `GPIO_IRQ_xxx` definitionsSubrata Banik
This patch removes the GPIO_IRQ_START and GPIO_IRQ_END definitions from itss.h for Alder Lake, Cannon Lake, Elkhart Lake, Jasper Lake, Meteor Lake and Tiger Lake. These definitions are no longer needed. TEST=Able to build and boot google/xol and google/karis. Change-Id: I60a08ba2c894fd1c1af6c6aef3ddc4a33ec63e76 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84182 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-04soc/intel/meteorlake: Remove unused pch_handle_sideband() functionSubrata Banik
This change removes the unused pch_handle_sideband() function from the Meteor Lake platform code. TEST=Able to build and boot google/rex. Change-Id: Idd14748aa1d917d6e88d738541a737c04a2c6a15 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2024-09-04tree: Drop unnecessary "true/false" commentsElyes Haouas
Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-02soc/intel/meteorlake: Hook up microcode from repositoryFelix Singer
Change-Id: I46021accacbb911d7a7ecfdbb52973a7da78f36e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-08-30soc/intel/meteorlake: Configure DDR5 Physical channel width to 64Arthur Heymans
A DDR5 DIMM internally has two channels each of width 32 bit. But the total physical channel width is 64 bit. This is the same fix as be5dc3daa "soc/intel/alderlake: Configure DDR5 Physical channel width to 64" Building with GCC LTO cought this buffer overflow when assigning SPD addresses to a buffer. Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-22soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdrCliff Huang
These field defines are SOC-specific. The AUX bias virtual wire field positons are shifted in PTL. In MTL SOC and older: 7:0 GROUP_ID Group ID in PCH GPIO 10:8 BIT_NUM Data bit Position in PCH GPIO 23:16 VW_INDEX VW Index in PCH GPIO In PTL SOC: 15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID 18:16 BIT_NUM Data bit Position in PCH GPIO 31:24 VW_INDEX VW Index in PCH GPIO BUG=361048817 TEST=boot to OS and use iotools to read AUX Bias Ctrl register to verify the group ID, bit number, and vw index. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83980 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-08-21soc/intel/meteorlake: Switch to SOC_INTEL_COMMON_DEBUG_CONSENTSubrata Banik
This patch replaces the SoC-specific config option `SOC_INTEL_METEORLAKE_DEBUG_CONSENT` with the generic `SOC_INTEL_COMMON_DEBUG_CONSENT`. Additionally, updates the FSP configuration to use the new generic config option. TEST=Able to build and boot google/rex0 without any functional impact while debugging. Change-Id: I657d20a38e15eee333a4e45c0c600736148173d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83961 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-20soc/intel/meteorlake/chip.h: Use boolean type where applicableMichael Strosche
Change-Id: I15dfd5ed0541352930c3b70252b3e536ad1e6efd Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-08-14soc/intel/adl,mtl/romstage/fsp_params: fix clock request warningFelix Held
If a root port doesn't use a clock request pin, we shouldn't check if this pin number, which defaults to 0 when not set, is already used. This fixes the following spurious warning that was previously printed for each external PCIe port which has the 'PCIE_RP_CLK_REQ_UNUSED' flag set and didn't set 'clk_req' to some unused clock request pin number: Found overlapped clkreq assignment on clk req 0 Tested on the cw-al-4l-v2.0 mainboard that uses an Alder Lake N100 SoC which I'm currently porting coreboot to. Also changing this for Meteor Lake, since they have the same implementation in their romstage fsp_params.c file Change-Id: I3ee66ca5ed5a2d06dfb68c45a50e11eb2b93daa0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-08-13soc/intel/mtl: enable FSP uGOP config in MTL for eSOLJayvik Desai
This patch updates the platform-specific Meteor Lake early sign-of-life config (SOC_INTEL_METEORLAKE_SIGN_OF_LIFE) with a generic ChromeOS eSOL config (CHROMEOS_ENABLE_ESOL) which uses the Intel FSP uGOP driver as an underlying technology for rendering eSOL screen. This patch does not change the binary or the system behaviour. BUG=b:352651132 TEST=Able to build google/rex and checked the config in output. Change-Id: Ib4589f52080229b1c83915b51272a042b7ac32cd Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83769 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26soc/intel/meteorlake: Remove unnecessary #if ENV_RAMSTAGESubrata Banik
TEST=Able to build google/rex. Change-Id: I0de87a2ff5ecb37f00ec745ad930e83f6356a3fe Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83637 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-26soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibilityRishika Raj
This change increases the DCACHE_BSP_STACK_SIZE from 512KB + 1KB to 512KB + 32KB, addressing a requirement specified by coreboot where stack usage is higher than 1KB alone. BUG=None TEST=None Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e Signed-off-by: Rishika Raj <rishikaraj@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83540 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-21soc/intel/meteorlake/chip.h: Drop unused PmTimerDisabled settingFelix Singer
Change-Id: I6155ec45408dca83573c86e6db1ead5a82a0d77a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18soc/intel/meteorlake: Remove p2sb.c from bootblock buildSubrata Banik
This patch removes `p2sb.c` from the bootblock build for the Meteor Lake platform. BUG=none TEST=Builds successfully for google/rex. Change-Id: Ib2beeee68bb20568888d4b555c2fa82e0bf0fd3c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-07-18soc/intel/meteorlake: Switch to common eSPI headerSubrata Banik
This patch updates Meteor Lake code to use the common eSPI header file(`intelpch/espi.h`) instead of the SoC-specific one. BUG=none TEST=Builds successfully for google/rex. Change-Id: Ibb37413bb6c925650f55b0dcf70e7483bf257888 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18soc/intel/meteorlake: Use common CAR API for cache reportingSubrata Banik
Replace the SoC-specific `report_cache_info()` function with the common `car_report_cache_info()` API from `car_lib`. This promotes code reuse and reduces SoC-specific implementation for cache reporting. BUG=none TEST=Builds and boots successfully on google/rex platform. Change-Id: Id5ffcab54232294ffa101f975d0ec51ac63f1910 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18soc/intel/mtl: Enable eSOL for x86_64 archSubrata Banik
This change removes the condition that SOC_INTEL_METEORLAKE_SIGN_OF_LIFE is only enabled for x86_32 arch. Now, it is safe to enable eSOL for x86_64 platform as well. BUG=b:346682156 TEST=Able to see eSOL on google/rex64. Change-Id: I825c988800ec303a8f37141f6487115b1c7c5d3a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83498 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-12soc/intel: Adapt crashlog IP to also support 64-bitSowmya Aralguppe
This patch extends the crashlog IP support beyond 32-bit mode to support Intel future generation SoCs, which may require crashlog support for 64-bit architectures. uintptr_t data type is used for Address pointers and void* for dereferencing BUG=b:346676856 TEST=Successfully built Meteor Lake (rex) and tested for google/rex0 and google/rex64 images. Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83106 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11soc/intel/meteorlake: Conditional selection of CSE Lite PSRSubrata Banik
This patch makes the selection of `SOC_INTEL_CSE_LITE_PSR` conditional on both `MAINBOARD_HAS_CHROMEOS` and `SOC_INTEL_CSE_LITE_SKU` being enabled. This ensures that CSE Lite PSR is only active when both ChromeOS is the target platform and CSE sync is performed inside coreboot. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I7199c034bbe6e7f077650417da67fa544f0b49d5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83396 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-11soc/intel/meteorlake: Conditionally update CSE sync UPDs in FSP-MSubrata Banik
This patch updates FSP-M UPDs conditionally to ensure CSE firmware updates and VGA initialization control only when `SOC_INTEL_CSE_LITE_SKU` config is enabled. This ensures eSOL rendering is tied to CSE sync performed in coreboot, preventing unnecessary setup when sync is deferred to the payload. Deferring CSE sync to the payload results in the depthcharge screen. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Iffdd4b1be4abba8c57e28542058a575cc6de674c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-06-26acpi: Rename acpi_create_dmar_drhdShuo Liu
For most of SoCs, DRHD is by default with the size of 4KB. However, larger sizes are allowed as well. Rename acpi_create_dmar_drhd to acpi_create_dmar_drhd_4k to support the default case while a later patch will re-add acpi_create_dmar_drhd with a size parameter. TEST=intel/archercity CRB Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-03soc/intel/meteorlake: Enable USB2 port reset message on Type-C portsJeremy Soller
Apply commit c6b65c1a811e ("soc/intel/alderlake: Enable USB2 port reset message on Type-C ports") to Meteor Lake. This change is added to address the issue of USB3 ports downgrading to high speed during low power modes and not returning back to super speed. The patch enables port reset event on USB2 ports. This event is is passed to USB3 upstream ports to upgrade back to super speed (USB3) after a downgrade during low power state. Change-Id: Iac702a8d8edd2b3b7e03abcac020be7e45335821 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82730 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-03soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetreeMichał Kopeć
The comment that the PchHdaAudioLink UPDs only configure GPIOs is incorrect. Setting this to 1 is needed to enable HDA audio link. Same exact situation as with Alder Lake in CL 71715. Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2024-05-31soc/intel: Fix pointer size mismatch errors in crashlogAppukuttan V K
The crashlog code in intel/common/block and meteorlake soc was casting integer addresses directly to pointer types, which caused compilation errors in x86_64 bit builds. This commit fixes the issue by using uintptr_t for casting integer addresses to pointer types before dereferencing. BUG=b:329034258 TEST=Successfully build Meteor Lake (rex) in both x86_32 and x86_64 modes. Change-Id: I2d0814a8b767270ec140341bfb51d0782469545d Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82481 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 buildsAppukuttan V K
EnableMultiPhaseSiliconInit upd is deprecated and has been removed starting with v2.4 of FSP specification. Multi-phase silicon initialization is mandatory for all FSP implementations compliant to v2.4. The following modifications are made: - In fsp_params.c and silicon_init.c EnableMultiPhaseSiliconInit update is guarded so that it will get included only if FSP2.4 is not selected. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Icdbf3bacc0a05975fc941b264fd400d74f506fce Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31soc/intel/meteorlake: Tailor FSP Version Selection for ArchitectureSubrata Banik
* Conditionally select FSP 2.4 when x86_64 support is available (HAVE_X86_64_SUPPORT). * Default to FSP 2.3 otherwise. * Adjust default FSP header path to align with architecture. BUG=b:242829490 TEST=Able to build google/rex in both 32-bit and 64-bit mode. Change-Id: Ib77a34c6bf7bca3485a197f109d1550ac3d51cc0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-31soc/intel/meteorlake: Enable eSOL without 64-bit supportSubrata Banik
This change allows eSOL to be enabled on production Meteor Lake silicon even when 64-bit support is not present. eSOL support is still TBD for 64-bit FSP hence, skip adding this support for 64-bit build. TEST=Able to build and boot google/rex64 w/o eSOL. Change-Id: I16762e5b74ae0aaa3c28730479a1fd9defc4d93c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82716 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-30vc/intel/fsp/mtl: Add x86_64 FSP V3471.91 headersAppukuttan V K
This commit introduces new header files of V3471.91 for the x86_64 architecture in the fsp2_0/meteorlake directory. FSP2.4 brings FSP 64-bits support and the soc Kconfig file has been updated to select this new header path when FSP2.4 is in use. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Ib41b57e794311db729ac65a968f562aa127e86c3 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-05-30vc/intel/fsp/mtl: Organize FSP headers into x86_32 directoryAppukuttan V K
This commit moves FSP V3471.91 header files for Meteor Lake into a new x86_32 directory to better organize the files based on the architecture. The Kconfig file has been modified accordingly to reflect the new paths of the relocated headers. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Id30186a8b1b5a9082f498e18a3378f5e9907b668 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82424 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-30soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibilityAppukuttan V K
This commit updates the type definitions for FSP parameters in the Meteor Lake platform to ensure compatibility with the FSP2.4 specification, that supports 64-bit builds for the first time and this also ensures that parameter types works for both 32-bit and 64-bit builds. - In fsp_params.c, FSPS_ARCH_UPD macro is changed to FSPS_ARCHx_UPD which supports FSP2.4 and older specifications. Special handling is added for FspEventHandler assignment to handle as the variable type is different in both cases. - In meminit.c, the type for SPD pointers is changed from uint32_t to efi_uintn_t to support both 32-bit and 64-bit builds. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82177 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21soc/intel/meteorlake: Add PsysPL2 configurationTony Huang
psys_pl2_watts is configured in SoC node of devicetree. Value represents Watts. BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot Change-Id: I9c4d62b93fc751db9e0ea04e475acb8861a844f8 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-07soc/intel/meteorlake: Determine TBT controllers exist by VID/DIDKane Chen
The original code uses TRE0-TRE3 register to determine whether or not the TBT controller exists. However, there is a remap in fsp could confuse the TRPx._STA. Ex: Disable TBT controller 0 on b:0 d:7 f:0 Enable TBT controller 1 on b:0 d:7 f:1 The FSP will do the remap and after the remap: TBT controller 1 is on b:0 d:7 f:0 TBT controller 0 is on b:0 d:7 f:1 This is becuase func 0 must exist per pci spec. However, the TRE0-TRE3 will not be remapped so that the ACPI TRPx._STA method could be confused. In such scenario, TRP0._STA will return 0x0, TRP1._STA will return 0xf which is wrong because TBT controller 1 is now at b:0 d:7 f:0 TEST=tested on rex and _TRPx._STA returns correctly. TBT function OK Change-Id: I54f2ea99cd1ec73dd0b71a6ba738aa927b0ae80f Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-05-07soc/intel/mtl: Fixed TBT PCIe devtree remappingKane Chen
The TBT PCIe devicetree settings are not remapped properly when TBT PCIe port 0 is disabled. This code refer SHA:58bc5d937 to remap the PCIe devtree settings properly in case of TBT PCIe port0 is disabled, TEST=Tested on screebo and found "Remapping PCIe Root Port #2 msg" showed up in coreboot log Change-Id: I7c7549ddf8ccdd67d7af7c69f51a84614cff9a03 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81841 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU DIDMichał Kopeć
Found in a Clevo V560TU with Intel Core Ultra 155H Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82071 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-11tree: Drop unused <timestamp.h>Elyes Haouas
Change-Id: Ic690a7543f8a1e072650917d7a1e9e3b9dc371a3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-04-11tree: Drop unused <timer.h>Elyes Haouas
Change-Id: Ib454330c5f584760c47ff0127a720cec5773b922 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-04-11tree: Drop unused <string.h>Elyes Haouas
Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81818 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09tree: Drop unused <delay.h>Elyes Haouas
Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30soc/intel: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I79b93b0ca446411e2a1feb65d00045e3be85ee8a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-17soc/intel/mtl: Enable RAMTOP caching at SoC level for MTL devicesSubrata Banik
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration at the SoC level for all MTL devices. This change streamlines the configuration process, avoiding redundant selections on individual mainboards. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot functionality on google/ovis and google/rex. Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-03-14vendorcode/edk2-stable202302: Remove wchar_t assertsArthur Heymans
Remove those MSVC compiler defaults checks so that the GCC defaults for wchar_t can be used. The FSP interface does not depend on wchar_t. TEST: the resulting binaries are the same for intel/mtlrvp Change-Id: I0ee1abc7e9ba46665838b63a6cfe0f4aa300114c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-03-13soc/intel/mtl: Improve functions in soc_info.cTyler Wang
Remove debug message since it's static information. Remove additional uint_8 varience and return below settings directly: 1. CONFIG_SOC_INTEL_USB2_DEV_MAX 2. CONFIG_SOC_INTEL_USB3_DEV_MAX 3. MAX_TYPE_C_PORTS 4. CONFIG_MAX_TBT_ROOT_PORTS 5. CONFIG_MAX_ROOT_PORTS 6. CONFIG_MAX_PCIE_CLOCK_SRC 7. CONFIG_SOC_INTEL_UART_DEV_MAX 8. CONFIG_SOC_INTEL_I2C_DEV_MAX 9. CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX BUG=none TEST=Build and test on rex/karis, system can boot to OS Change-Id: I26e882d2d9dcbef84718924aaab3864d89c58f39 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-03-08drivers/intel/fsp2_0: Add "silicon" to the multiphase callback nameJeremy Compostella
The `platform_fsp_multi_phase_init_cb' callback is specific to FSP-S, let's rename it 'platform_fsp_silicon_multi_phase_init_cb' to avoid any confusion. Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-01soc/intel/meteorlake: Select MRC_CACHE_USING_MRC_VERSIONJincheng Li
MRC_CACHE_USING_MRC_VERSION is irrelevant to the EDK2 binding version and should not be enabled under specific version conditions, so select this at SoC level. Change-Id: I10594df7c8fdc5cfe9b68975e01ae65859735544 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80728 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-18soc/intel/mtl: Skip RW CBFS ucode update if RO is lockedSubrata Banik
This patch eliminates coreboot from loading microcode from RW CBFS (when the RO descriptor is locked, which indicates a fixed RO image) because the kernel can already patch the microcode on BSPs and APs while booting to OS. This may be a chance to lower the burden on the AP FW side because patching microcode on in-field devices is subject to firmware updates, which are rarely published and, if required, must go through the firmware qualification testing procedure (which is costly, unlike kernel updates for ucode updates). 1. The FIT loads the necessary microcode from the RO during reset. 2. Reloading microcode from RW CBFS impacts boot time (~60ms, core-dependent). 3. The kernel can still load microcode updates. ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is sufficient for initial boot, and the kernel can apply updates later. BUG=none TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode loading when RO is locked. Change-Id: Ia859809970406fca3fa14e6fa8e766ab16d94c8a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2024-02-18soc: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-16soc/intel/mtl: Double the `IgdDvmt50PreAlloc` UPD size to 128MBSubrata Banik
This patch increases the IgdDvmt50PreAlloc value as per Intel recommendation starting with GFX PEIM 103x. TEST=Able to build and boot google/rex. Change-Id: I236b38a1ac5efbfcd23e373c09204d8a07b97618 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80406 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-02-13soc/intel/meteorlake: Leverage IA common code for range calculationsSubrata Banik
Improves code maintainability and potentially reduces redundancy by using the IA common implementation. Additionally, drop the unused macros from SoC local. TEST=Build and boot successful on google/screebo. Change-Id: Ie0baae1d3b0093389649dee3531902c5e86c02fe Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80404 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-12soc/intel/cmn/sa: Refactor SA common codeSubrata Banik
Leverages common SA header definitions for Host Bridge registers. Renames DSM_BASE_ADDR_REG to BDSM and DPR_REG to DPR for brevity. Additionally, made some minor code alignment corrections while adding newer macros in the header file. TEST= Build and boot successful on google/screebo. Change-Id: I476f213d75a0978336b3749a5ba1499107eb2238 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-24soc/intel: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib479b93b7d0b2e790d0495b6a6b4b4298a515d9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80073 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-22soc/intel/meteorlake: Fix system hang by enabling SMI handlingKane Chen
Issue: System hang occurred due to unhandled SPI synchronous SMI, triggered by LOCK_ENABLE bit and WPD assertion. Solution: Enabled SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE configuration to allow the system to handle and clear SPI synchronous SMI. BUG=b:306267652 TEST=Cold reboot test on 20 google/screebo by ODM, all passed w/o hang. Change-Id: Ie1f096f8eda4adcf1627e44afa517b02adddad76 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-17Reland "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi
This reverts commit acbc4912375085a099c2427def464d6e481f2a90. Reason for revert: CB:79525 fixes the issue that led to the revert by not maintaining the heap in the SMM-stored copy of ramstage at all. Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11soc/intel/meteorlake: Enable FSP logo support by defaultSubrata Banik
Enables FSP logo support for Meteor Lake SoC config, covering both Intel Meteor Lake RVP and ChromeOS devices. Applies HAVE_FSP_LOGO_SUPPORT configuration only for platforms with native FSP support. Ensures successful builds and boots for google/rex and intel/mtlrvp. BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex and intel/mtlrvp Change-Id: Ic99bfdc2d33db48bdb015525981c1ef76df8203b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79859 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-09soc/intel/mtl: Override the `SOC_PHYSICAL_ADDRESS_WIDTH` as integerSubrata Banik
This patch enforces consistent override handling for integer `SOC_PHYSICAL_ADDRESS_WIDTH` config Change-Id: Ib5bdfdb8c2689803c9d3c2bfd353609edae91ab3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-02soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verificationJeremy Compostella
Enabling SSE2 accelerated RSA signature verification saves 4.7 ms of boot time. | modpow() function call | original | SSE2 Algorithm 2 | |----------------------------+----------+------------------| | coreboot/verstage - step 1 | 6.644 | 3.042 | | coreboot/verstage - step 2 | 1.891 | 0.757 | |----------------------------+----------+------------------| | Total (ms) | 8.535 | 3.799 | BUG=b:312709384 TEST=modular exponentiation is more than twice faster on rex0 Change-Id: I382e62a765dbf2027c4ac54d6eb19a9542a8c302 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79291 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22soc/intel/meteorlake: Fix SOC_PHYSICAL_ADDRESS_WIDTH to 42Jeremy Compostella
Meteor Lake CPUs physical address size is 46 if TME is disabled, 42 if TME is enabled but Meteor Lake SoC physical address size is always 42. BUG=b:314886709 TEST=MTRR are aligned between coreboot and FSP Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79666 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22Revert "soc/intel/meteorlake: Set build time physical address reserved bits"Jeremy Compostella
This reverts commit 533efb23083afd721d4c268ce0ee8e863e13689a. BUG=b:314886709 Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79664 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-20soc/intel/common,mtl: Refactor BERT generation flow for crashlogPratikkumar Prajapati
With earlier flow, a chunk of CBMEM region was allocated for each SRAM e.g., PUNIT SRAM, SOC PMC SRAM and IOE PMC SRAM. Then entire SRAM content was copied to dedicated CBMEM region. Later in acpi_bert.c, the BERT table was getting created for each chunk of CBMEM. This flow was not considering creating separate entries for each region of crashlog records. It resulted in only the first entry getting decoded from each SRAM. New flow aims to fix this issue. With new flow, a simple singly linked list is created to store each region of crashlog records from all SRAMs. The crashlog data is not copied to CBMEM. The nodes are allocated dynamically and then copied to ACPI BERT table and then freed. This flow also makes the overall crashlog code much simpler. BUG=b:298234592 TEST=With this change decoding crashlog show comprehensive details, tested on REX. Change-Id: I43bb61485b77d786647900ca284b7f492f412aee Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78257 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20soc/intel/meteorlake: Add Acoustic Noise Mitigation UPDsSubrata Banik
This patch allows to override acoustic noise mitigation FSP UPDs: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate BUG=b:312405633 TEST=Able to override the acoustic noise UPDs. Change-Id: I5295e6571121c92f363e6fd4bcb3c8335c4fedee Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79302 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-18soc/intel/mtl: Adaptively disable 3-strike error for QS siliconSubrata Banik
This patch provides a way to mask the 3-strike error on Intel Meteor Lake SoC platform across pre-prod and prod SoC. This patch decouples MSR selection for 3-strike error disablement, ensuring compatibility across SoC types. Without the correct MSR been programmed the SoC platform is unable to disable 3-strike error. BUG=b:314883362 TEST=Disable the 3-strike on google/screebo with QS silicon. Change-Id: I5363102deea67c44c9433a3f66c92badb0d0f182 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79473 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-11soc/intel/meteorlake: Add entries to eventLog on invocation of early SOLSubrata Banik
This patch records early signs of user activity during CSE firmware synchronization or MRC (re)training events in the event log (ELOG_TYPE_FW_EARLY_SOL). These can be used to ensure persistence across global reset (e.g. after CSE sync) so that they can be later retrieved in order to build things such as test automation ensuring that we went through the SOL path/display initialized. BUG=b:279173035 TEST=Verified on google/rex, event shows in eventlog after CSE sync and/or MRC. Scenario #1: While performing MRC update 1 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown 2 | 2023-11-08 | Memory Cache Update | Normal | Success 3 | 2023-11-08 | System boot | 9 4 | 2023-11-08 | ACPI Wake | S5 Scenario #2: While performing CSE update/downgrade 11 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown 12 | 2023-11-08 | System boot | 13 Scenario #2: While performing both MRC and CSE upgrade 16 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown 17 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown 18 | 2023-11-08 | Memory Cache Update | Normal | Success 19 | 2023-11-08 | System boot | 16 20 | 2023-11-08 | ACPI Wake | S5 Change-Id: Idfa6f216194fd311bb1a57dd7c86fe7446a3597c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78983 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-11soc/intel/mtl: Display Sign-of-Life message using FSP-MJeremy Compostella
Meteor Lake Firmware Support Package (FSP-M) for ChromeOS includes an pre-memory graphics driver which can be leveraged to display a text message thanks to the following FSP-M UPD (Updateable Product Data): - VgaInitControl (bitfield): Bit 0: Turn on graphics, setup VGA text mode and display `VgaMessage' text centered on the screen. Bit 1: Clear text and tear down VGA text mode and graphics before returning from FSP-M. - VbtPtr (address): Pointer to the VBT (Video BIOS Tables) binary. - VbtSize (unsigned int): Size of the VBT binary. - LidStatus (boolean): Due to limited resources at early boot stages, the text message is displayed on a single monitor. The lid status helps decide which display is the most appropriate. 0: Lid is closed: show the text message on the external display if available, do not display anything otherwise. 1: Lid is open: show the message on the internal display if available, use an external display if available otherwise. - VgaMessage (string): Text message to display. If the `SOC_INTEL_METEORLAKE_SIGN_OF_LIFE' flag is set, coreboot configures the UPDs above to display a text message during memory training and CSME update. The text message can be configured via the locale text mechanism using the `memory_training_desc' name. The `SOC_INTEL_METEORLAKE_SIGN_OF_LIFE' selects the LZ4 compression algorithm for VBT because LZMA decompression is not available in romstage by default and adding LZMA support increases the romstage binary size more than the VBT binary is reduced. BUG=b:279173035 TEST=Text message is displayed during memory training on a rex board Change-Id: I8e7772582b1895fa8e38780932346683be998558 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78244 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11soc/intel/meteorlake: Disable MarginLimitCheck and RMC UPDsKilari Raasi
By default MarginLimitCheck and RMC UPDs are enabled in FSP which enables fast and cold boot retraining causing the boot time increase. So, disabling the same UPDs to fix it. Change-Id: Ib15d37dbe177f31590f23de4e239a2e82abf1335 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-21soc/intel/mtl: Keep SOC_INTEL_COMMON_BASECODE_RAMTOP for non-ChromeOSSubrata Banik
This patch guarantees that non-ChromeOS platforms continue to enable early caching. ChromeOS devices, on the other hand, control this configuration through the motherboard configuration based on the underlying SoC. BUG=b:306677879 TEST=Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for google/rex. Change-Id: I412b2b6a807dc0f5f2632f0fbd56bd37689dead3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-10soc/intel/meteorlake: Set DTT PCI device IRQ to INT_A/PIRQ_AJeremy Compostella
The Dynamic Tuning Technology (DTT) device IRQ is not programmable and is INT_A/PIRQ_A (IRQ 16). Reference: Meteor Lake U/H and U Type4 External Design Specification External Design Document (657165) TEST=Linux driver successfully uses IRQ 16 on rex. Without this patch it was binding IRQ 18 but interrupts were going to IRQ 16. Change-Id: I2cbb9dd41f27c40a29346be325bb9c46d1061afb Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-07Revert "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi
This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6. Reason for revert: It breaks wakeup from suspend on a bunch of boards. While this approach of eyeballing "correct" values by chipset _should_ be fixed, it should also be accompanied by compile time verification that the memory map works out. Since nobody seems to care enough, let's just revert this, instead of keeping the tree broken for a bunch of configurations. Change-Id: I3cd73b6ce8b15f06d3480a03ab472dcd444d7ccc Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78850 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-04soc/intel/meteorlake: Consolidate settings for enabling tracehubKane Chen
To get tracehub working, it requires few settings such as SOC_INTEL_METEORLAKE_DEBUG_CONSENT=2 and enable tracehub device in dev tree. This commit binds all tracehub related settings to Kconfig, so that users only need to enable SOC_INTEL_COMMON_BLOCK_TRACEHUB TEST=boot on screebo and test tracehub device exists and working Change-Id: Ie830fe2fd38e3456497bea37fe42ca60d26ca305 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-02Revert "soc/intel/{tigerlake,meteorlake}: Check ITBT FW version"Ravi Sarawadi
This reverts commit 2e10a6d6f3ec46bcaf75bd066319d51f001be764. Reason for revert: The FW version check is not supported except for ADL platform. Reverted change broke S0ix functionality; the original CL was added as HW W/A for ADL ONLY. BUG=b:306214725 TEST=S0ix cycles on Rex with TBT Device attached. Change-Id: Ib8eb11d36eac4e1c94a3349386442fa3eeeaef37 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78457 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-02drivers/intel/gma/opregion: Use CBFS cache to load VBTJeremy Compostella
Thanks to x86 CBFS cache support, we can leverage cbfs_map() function to load the VBT binary regardless of if it is compressed or not. Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-01soc/intel/meteorlake: Adjust Power State Current 2 thresholdJeremy Compostella
VccSA Power State 2 (PS2) current threshold has be adjusted to 10A to improve PS2 residency which reduces Voltage Regular (VR) power loss. BUG=b:308002192 TEST=power and performance analysis shows a positive Load Line result Change-Id: I2da2b05de8a04f91dacaa55062165c4351422865 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-01soc/intel/meteorlake: Add power limits for 4+8 28W SOC SKUCurtis Chen
This commit adds power limit settings for 4+8 28W SOC sku and renames MTL_P_682_CORE to MTL_P_682_482_CORE since they are sharing same 28W settings. BUG=b:306677879 TEST=boot on rex with 4+8 SOC and power limit settings are correct Change-Id: Icb5fc2b13e8510f89c03927439431190439a3a94 Signed-off-by: Curtis Chen <curtis.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78796 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-28soc/intel/meteorlake: Expose In-Band ECC UPD config to mainboardMarx Wang
Meteor Lake has a UPD config called In-Band ECC(IBECC) which uses a part of the system DRAM to store the ECC information. There are a few UPD parameters in FSP-M to configure this feature as needed. This patch adds code to expose these parameters to the devicetree so that they can be configured on the mainboard level as needed. Change-Id: Ice1ede430d36dff4175a92941ee85cc933fa56d5 Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-28soc/intel/meteoerlake: Add power limits for 2+4 15W SOC SKUKane Chen
This commit adds power limit settings for 2+4 15w SOC sku and renames MTL_P_282_CORE to MTL_P_282_242_CORE since they are sharing same 15w settings. BUG=b:306543967 TEST=boot on rex with 2+4 SOC and power limit settings are correct Change-Id: Id738303d1652f964142f8f27110426d6b84609bf Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78495 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-24soc/intel/meteorlake: Add PsysPmax configurationJakub Czapiga
psys_pmax_watts is configured in SoC node of devicetree. Value represents Watts the PSU provides. Zero means automatic/default configuration (not optimal). BUG=b:289853442 TEST=Build google/rex/ovis4es target board Change-Id: I69afa06110254f6384352c062891c0c9c0b23070 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76796 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20soc/intel/meteorlake: Set build time physical address reserved bitsJeremy Compostella
Meteor Lake TME bits [42-45] are reserved regardless of if the part supports TME or not. On a device with TME fused off, we noticed some reboot hangs which have been narrowed down to internal IP routing issues when the IA accesses the Input Output Manager (IOM) which is mapped at 0x3fff0aa0000 (0x3ff upper 32 bits). It turns out since TME is fused off, coreboot uses the full physical address size reported by CPUID MAXPHYADDR (46 bits). Therefore, it allocates thunderbolt memory range on 46 bits (0x3fff upper 32 bits). Since 4 of these bits are actually reserved, it seems that this address range is "stripped down" to 42 bits (=> 0x3ff upper 32 bits) resulting in potential conflict with other devices such as IOM. BUG=b:288978352 TEST=No reboot issue on rex with TME fused off Change-Id: I96ba23ab304257003c0413243d3ac8129ce31743 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78452 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20device/device.h: Rename pci_domain_scan_busArthur Heymans
On all targets the domain works as a host bridge. Xeon-sp code intends to feature multiple host bridges below a domain, hence rename the function to pci_host_bridge_scan_bus. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-10-19soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QSRavi Sarawadi
Within TBT PCIe, following register offsets have been updated for production silicon. Update ASL with new offsets. 1. MPC - Miscellaneous Port Configuration Register 2. RPPGEN - Root Port Power Gating Enable 3. SMSCS - SMI/SCI Status Register BUG=306026121 TEST= Check TBT PCIe Tunnel creation and device enumration. Change-Id: I0497f7108ef5046c2694aece232263582514a0c5 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-19soc/intel: Improve CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_HZ useJeremy Compostella
Commit bd9c562a9e0c6af65f5e798a17ba9a55892ef082 ("acpi: Configure slp-s0 residency counter frequency in LPIT table") led to jenkins reporting the following error: !!!!! Error: defined(CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_HZ) used at src/include/acpi/acpi.h:457. Symbols of type 'hex' are always defined. Since hex Kconfig are always defined there is no need to test it being defined but also no need to handle zero or non-zero values. In addition: 1. This config was defined in Meteor Lake specific Kconfig file while it should actually be define closer to where it is being used (here soc/intel/common/block/acpi/Kconfig) and only set by the SoC Kconfig. 2. Once moved and under control of `SOC_INTEL_COMMON_BLOCK_ACPI_LPIT' gating (lpit.c), the Kconfig name needed to be adjusted to better fit its use. 3. Make Meteor Lake Kconfig sets the config but does not define it anymore. TEST=LPIT ACPI table Counter Frequency field is set to 0x2005 on rex Change-Id: I2083c9209e61be6180cca2c9f74097e2f4b4ce9a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78458 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-18soc/intel/mtl: Set slp-s0 counter frequencySukumar Ghorai
System sleep time (SLP_S0 signal asserted) is measured in ticks, for Meteor Lake soc in 122us (i.e. ~8197Hz) granularity/ticks. Change-Id: I1e95cd69e941d4d72d5c36a07660ca07ee2499ba Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-18soc/intel/{adl, mtl}: Avoid redundant display init by joining to MBUSSubrata Banik
This patch ensures that the IGD joins the MBUS when the firmware splash screen feature is enabled (aka BMP_LOGO config is enabled). For ChromeOS platform, it prevents the i915 driver from reinitializing the display, which can save up to 75ms-80ms of boot time and eliminate a brief period of blank screen between the firmware splash screen and the OS login prompt. BUG=b:284799726 TEST=Able to build and boot google/rex. Change-Id: I36af167afa902053a987602d494a8830ad9b1b1a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-11Kconfig: Bring HEAP_SIZE to a common, large valuePatrick Georgi
We have a tiny HEAP_SIZE by default, except when we don't, and mainboards that override it, or not. Since memory isn't exactly at a premium these days, and unused heap doesn't cost anything extra, just crank it up to the highest value we have in the tree by default and remove all overrides. Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78270 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-09soc/intel/meteorlake: Reserve IOE P2SB MMIO correctlyKane Chen
The original code only reserves IOM mmio, but there is other asl code that requires to program ioe p2sb mmio such as IOE PCIE clk request control. See \_SB.ECLK.CLKD in src/soc/intel/common/acpi/pcie_clk.asl TEST=as before: suspend_stress_test 50 cycle pass, type-c display OK on screebo Change-Id: Ie55f7975277b390f776e44596c42e426ba9cd235 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78252 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-07mb/google/{rex,ovis}: Disable package C-state auto demotionSukumar Ghorai
Package C-state auto demotion feature allows hardware to determine lower C-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter below PC8 state and additional power savings ~30mW in Local-Video-Playback scenario. BUG=b:303546334 TEST=Local build successfully & Boot to OS successfully - Also check platform enter PC8 state in local video playback - before this change: # iotools rdmsr 0 0xE2 -> 0x0000000060008008 - After # iotools rdmsr 0 0xE2 -> 0x0000000000008008 Change-Id: Ia4cf4a7cb6bd5eaae26197b55f9385c078960d7b Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78250 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-10-04soc/intel: Select GMA v2 for ADL, MTL, TGL to reflect port/pipe defsSubrata Banik
Intel GFX IP TRANS_DDI_FUNC_CTL register bit definitions have changed since Tiger Lake. This register is used to map ports and pipes to display controllers, so reflecting the correct status is important for detecting physical display end point devices. This patch ensures that ADL, MTL, and TGL SoCs choose GMA version 2 to properly reflect the updated port and pipe register definitions. BUG=b:299137940 TEST=Build and boot google/rex successfully. Change-Id: Ie2082747d18a5f136f410b1019be4d6c801617b1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-04soc/intel/mtl: Select SOC_INTEL_CSE_LITE_PSR config for MeteorlakeKrishna Prasad Bhat
During CSE firmware downgrade, data is cleared. To preserve PSR data during downgrade, it needs to be backed up. Select SOC_INTEL_CSE_LITE_PSR config to ensure PSR backup related flow is executed on CSE Lite SKU. BRANCH=None BUG=b:273207144 TEST=Verify CSE firmware upgrade/downgrade on rex. Change-Id: I39af029a5f0c018a5db3ac68191764abfa9518ac Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76115 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04soc/intel/mtl: Override SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSETKrishna Prasad Bhat
CSE firmware downgrade and PSR data backup flows involve global resets, there is a need to track the PSR data backup status across resets. In the subsequent patches, a CMOS structure to store PSR back-up status will be added. The current SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET of 68 can only store cse_specific_info, as ramtop is at offset 100 and PSR back-up status structure will not be able to fit within the range. This patch overrides the SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET to 161 to accommodate all CSE related info in adjacent CMOS memory. BUG=b:273207144 TEST=Verify CSE RW FW versions are stored in CMOS memory in rex. Change-Id: I8bae5245f93b99be15b4e59cfeffbc23eec95001 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78054 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04soc/intel/mtl: Call cse_fill_bp_info early in romstageKrishna Prasad Bhat
Intel Platform Service Record(PSR) will be enabled on Meteor Lake platforms. cse_fw_sync actions happen in ramstage when PSR is enabled. To avoid the boot time penalty of sending the cse_get_bp_info in ramstage, call cse_fill_bp_info to get cse_bp_info response early in romstage and store in cbmem. This data can be later used in ramstage. BUG=b:273207144 TEST=Verify cse_bp_info is filled in romstage in rex. Change-Id: Ic0e8fb34f21ff07e182a7b848d38e9d329010028 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-23soc/intel/meteorlake: Reduce memory test sizeSubrata Banik
Enable upd to reduce size of the memory test. BUG=b:301441204 TEST=Able to build and boot google/rex. w/o this patch: 951:returning from FspMemoryInit 650,922 (79,560) w/ this patch: 951:returning from FspMemoryInit 618,490 (45,621) Change-Id: I903591ec749d270a98895dafb2d8f8d0b287c26a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78067 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-23soc/intel/meteorlake: Hook up UPD LowerBasicMemTestSizeSubrata Banik
Hook the newly exposed LowerBasicMemTestSize UPD up so that boards can configure it via devicetree. BUG=b:301441204 TEST=Verified by enabling/disabling the UPD on google/rex. Change-Id: Iec466aeaebd72f222d97f720a85bbb8c27e26325 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78066 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-20soc/intel/meteorlake: Add configs for pre-production siliconSubrata Banik
Certain Intel Meteor Lake specific features are only enabled in production silicon (not available in early SoC aka pre-production silicon). - SPI usage for production SoC is much optimized compared to pre- production silicon. - MIPI driver requires a way to identify between pre-prod vs prod silicon. This patch adds config options to select the Pre-Production aka Engineering Silicon (ES). The mainboard users can specify which underlying SoC is being used for the target platform. BUG=b:300652989 TEST=No change in the functionality, just added new configs. Change-Id: I60fe11c1151a3a6c290cd0105eb570cb78e81797 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2023-09-20soc/intel/meteorlake: Enable crashlogPratikkumar Prajapati
Enable SOC_INTEL_CRASHLOG and SOC_INTEL_IOE_DIE_SUPPORT Kconfig options. BUG=b:262501347 TEST=Able to build google/rex. Able to trigger and decode crashlog. Change-Id: I4beef7393090889fde8d67827035c3b57a3dbb34 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 20:43:46 +0000