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path: root/src/soc/intel/jasperlake/pmc.c
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2023-07-12soc/intel/*/pmc.c: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I852d6daebdcb8461c18e7c0eaf1c54ad7c59c0c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-11-08soc/intel: Use `PWRMBASE` over static `Index 0` for PMCSubrata Banik
This patch replaces static index 0 for PMC read resources with PCI configuration offset 0x10 (PWRMBASE). TEST=Able to build and boot Google, Rex to OS. Without this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 With this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iee2523876a8045e70effd5824afc327d1113038b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-06-29soc/intel/jasperlake: Fix PMC read_resources callbackTim Wawrzynczak
The `limit` field for the PMC fixed BAR was incorrectly set to the `base + size + 1`, where it should be `base + size - 1`, to correctly tell the allocator the limit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Icf51333f438ce2597c008b48305cf5816dacd3f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65461 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15soc/intel/*/pmc: Add `finalize` operation for pmcSubrata Banik
This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs, i.e., Ready to Boot and End Of Firmware. Additionally, move the PMCON status bit clear operation to `.final` ops to cover any such chances where FSP-S Notify Phase or any other later boot stage may request a global reset and PMCON status bit remains set. BUG=b:211954778 TEST=Able to build brya with these changes. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a0b869849d5d8c76031b8999f3d28817ac69247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2021-10-17soc/intel: implement ACPI timer disabling per SoC and drop common codeMichael Niewöhner
Since it's just a one-liner, implement disabling of the ACPI timer in soc code. This reduces complexity. Change-Id: I434ea87d00f6e919983d9229f79d4adb352fbf27 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel: move disabling of PM Timer to SoC PMC codeMichael Niewöhner
Move disabling of PM Timer to SoC PMC code. The original reason for placing that in `finalize` [1] was FSP hanging due to use of the PM timer without enabling timer emulation first in coreboot, which was added later [2]. [1] commit 6c1bf27dae (intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown) [2] commit f004f66ca7 (soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs) Change-Id: I354c3aea0c8c1f8ff3d698e0636932b7b76125f7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-29soc/intel/{cnl,jsl,tgl,ehl,adl}: rename PMC device init/enable callbacksMichael Niewöhner
The current names of the PMC init/enable callbacks are very confusing. Rename them. Change-Id: I69f54f3b4e1ea9a9b4fa5c8dd9c0d454d7cd1283 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-10soc/intel/jasperlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch jasperlake boards to this method. soc/intel/jasperlake: Switch to acpigen PEPD Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-07soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXITKane Chen
On tgl, we noticed system hang if a shutdown is triggered before fsps. The dut is unable to shutdown properly due to tcss is stuck before tcss_init in fsps. This change enable power button smi on jsl, tgl, adl after fsps. it can also prevent a shutdown failure due to lack of fsps init on certain ip. BUG=b:186194102, b:186815114 TEST=Power on the system and pressing power button repeatedly doesn't cause the system hang during shutdown. Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-21soc/intel: Move pmc_soc_set_afterg3_en() to pmutil.cAngel Pons
Commit 2c26108208e4aa48de21be576ab6cad9286d7934 moved this function to pmutil.c for Tiger Lake. Do this to all other platforms for consistency. For Skylake, __SIMPLE_DEVICE__ preprocessor guards are no longer needed. With this change, pmc.c is only needed in ramstage. Adjust Makefile.inc accordingly, and drop ENV_RAMSTAGE guards from Skylake. Change-Id: I424eb359c898f155659d085b888410b6bb58b9ed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-08-24soc/intel/jasperlake: Run pmc_set_acpi_mode() during .init in pmc_opsKane Chen
pmc_set_acpi_mode will set EC SMI mask to 1 in the end. However google_chromeec_events_init will clear EC SMI mask. If google_chromeec_events_init is ran after pmc_set_acpi_mode, the EC SMI mask will be 0 in depthcharge and causes lidclose function not working. So, pmc_set_acpi_mode() should run after google_chromeec_events_init. This code is mainly from CB:42677 BUG=b:16338215 TEST=Close lid in depthcharge and the dut can be shutdown on waddledoo. Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: I0f06e8b5da00eb05a34a6ce1de6d713005211c08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-06-07soc/intel/jasperlake: Add JSL PMC as 'hidden' PCI deviceTim Wawrzynczak
This change allows treating the PMC as a 'hidden' PCI device on Jasper Lake, so that the MMIO & I/O resources can be exposed as belonging to this device, instead of the system agent and LPC/eSPI. Change-Id: Ie07987c68388d03359c43f64a849dc6e3f94676e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06soc/intel/jasperlake: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I2efdeb224c478995d393aa3eaac762c876832391 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-03-28soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper LakeAamir Bohra
This is a follow-up patch to initial copy patch for Jasper Lake SoC. Remove all Tiger Lake specfic code from Jasper Lake SoC code. BUG=b:150217037 Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-28soc/intel/jasperlake: Add Jasper Lake SoC supportAamir Bohra
This is a copy patch from Tiger Lake SoC code. The only changes done on top of copy is changing below configs: 1. SOC_INTEL_TIGERLAKE -> SOC_INTEL_TIGERLAKE_COPY 2. SOC_INTEL_JASPERLAKE -> SOC_INTEL_JASPERLAKE_COPY 3. SOC_INTEL_TIGERLAKE_BASE -> SOC_INTEL_TIGERLAKE_BASE_COPY We started with initial assumption that JSL and TGL can co-exist. But now we see the SoC code in Tiger Lake is relying on too many compile-time directives to make two SoCs co-exist. Some of the differences are listed below: -> Kconfig: Multiple Kconfig options using if SOC_INTEL_{TIGERLAKE/JASPERLAKE} -> GPIO: GPIO communities have their own differences. This requires conditional checks in gpio.asl, gpio.c, gpio*.h, pmc.h and gpio.asl -> PCI IRQs: Set up differently for JSL and TGL -> PCIe: Number of Root ports differ. -> eMMC/SD: Only supported on JSL. -> USB: Number of USB port are different for JSL and TGL. -> Memory configuration parameters are different for JSL and TGL. -> FSP parameters for JSL and TGL are different. The split of JSL and TGL SoC code is planned as below: 1. Copy Tiger Lake SoC code as is, and change SoC Kconfig to avoid conflicts with current mainboard builds. 2. Clean up TGL code out of copy patch done in step 1. Make it JSL only code. The SoC config still kept as SOC_INTEL_JASPERLAKE_COPY. 3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can bind to SoC code from soc/intel/jasperlake. This step establishes Jasper Lake as a separate SoC. 4. Clean up current JSL code from TGL code. This step establishes Tiger Lake as a separate SoC. BUG=b:150217037 Change-Id: I9c33f478a2f8ed5e2d8e7815821d13044d35d388 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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