| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-06-03 | soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND register | Elyes HAOUAS |
| 2020-06-02 | {icelake,jasperlake,skylake,tigerlake}/bootblock.c: Clean up includes | Elyes HAOUAS |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-04-28 | soc/intel/jasperlake: Add new MCH device ids | Maulik V Vaghela |
| 2020-04-06 | soc/intel/jasperlake: Use SPDX for GPL-2.0-only files | Angel Pons |
| 2020-03-28 | soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake | Aamir Bohra |
| 2020-03-28 | soc/intel/jasperlake: Add Jasper Lake SoC support | Aamir Bohra |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |