| Age | Commit message (Expand) | Author |
|---|
| 2021-01-31 | soc/intel/*: drop incomplete and unneeded check for DMI SRLOCK | Michael Niewöhner |
| 2021-01-25 | soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroring | Michael Niewöhner |
| 2020-12-09 | soc/intel/common/dmi: Move DMI defines into DMI driver header | Srinidhi N Kaushik |
| 2020-11-29 | soc/intel: Configure P2SB before other PCH controllers | Furquan Shaikh |
| 2020-08-07 | soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE | Subrata Banik |
| 2020-07-26 | soc/intel/jasperlakelake: Rename pch_init() code | Usha P |
| 2020-06-03 | soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND register | Elyes HAOUAS |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-04-06 | soc/intel/jasperlake: Use SPDX for GPL-2.0-only files | Angel Pons |
| 2020-03-28 | soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake | Aamir Bohra |
| 2020-03-28 | soc/intel/jasperlake: Add Jasper Lake SoC support | Aamir Bohra |
