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2020-10-28soc/intel: deduplicate ACPI timer emulationMichael Niewöhner
The code for enabling ACPI timer emulation is the same for the SoCs SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to common code. APL differs in not having the delay settings. However, the bits are marked as "spare" and BWG mentions there are no "reserved bit checks done". Thus, we can write them unconditionally without any effect. Note: The ACPI timer emulation can only be used by SoCs with microcode supporting CTC (Common Timer Copy) / ACPI timer emulation. Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-26soc/intel/icl: enable common CPU codeMichael Niewöhner
Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which gets used in CB:45535 and CB:45536 for CPPC entries generation. Note: This also retrieves the VMX Kconfig and enables it by default, like done for SKL and CNL already. Since FSP always set the feature config lock, SET_IA32_FC_LOCK_BIT gets selected statically by the SoC to reflect this in menuconfig. Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45826 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-26soc/intel: drop unneeded ISST configuration codeMichael Niewöhner
The code configuring ISST (Intel SpeedShift Technology) sets the ISST capability bits in CPUID.06H:EAX. It does *not* activate HWP (Hardware P-States), which shall be done by the OS only. Since the capability is enabled by default (opt-out), there is nothing to do for us in the enabled-case. Practically speaking, there is no value at all in disabling the capability, since one can configure the OS to not enable HWP if that is desired. The two other bits for EPP and HWP interrupt that were set by the code are not set anymore, too. It was tested, on three platforms so far (CML-U, KBL-H, SKL-U), that these are set as well by default in the MSRs reset value (0x1cc0). To reduce complexity and duplicated code without actual benefit, this code gets dropped. The remaining dt option will be dropped in CB:46462. Test: Linux on Supermicro X11SSM-F detects and enables HWP: [ 0.415017] intel_pstate: HWP enabled Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46460 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26src: Include <arch/io.h> when appropriateElyes HAOUAS
Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24{cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. This change just moves the code. Rework is done in CB:46588. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21soc/intel: convert XTAL frequency constant to KconfigMichael Niewöhner
This converts the constant for the XTAL frequency to a Kconfig option. Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21soc/intel/common: add Kconfig for PM Timer emulation supportMichael Niewöhner
Add a Kconfig for SoCs to indicate PM ACPI timer emulation support and select it by the appropriate SoCs. This Kconfig gets used in the follow-up changes. Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19soc/intel/*: drop useless XTAL shutdown qualification codeMichael Niewöhner
The XTAL shutdown (dis)qualification bit already unconditionally gets set to 1 by FSP for these platforms, making this code redundant. Change-Id: I7fa4afb0de2af1814e5b91c152d82d7ead310338 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46016 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12soc/intel: Configure PAVP at compile-timeBenjamin Doron
Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. Per the FSP default, this was always being enabled previously. Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08soc/intel: Make use of common gfx.aslSubrata Banik
Add gfx.asl file for all IA SOCs to allow for graphics-related ACPI devices and methods. TEST=Able to build and boot TGL platform Dump and disassemble DSDT, verify GFX0 device present as below Device (GFX0) { Name (_ADR, 0x00020000) // _ADR: Address } Change-Id: I5560e900a77872552df1064dc3b7a8148e35d682 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik
This patch moves platform.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify _PIC method present inside common platform.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/{cnl,icl,skl}: Convert 'platform.asl' to ASL 2.0 syntaxSubrata Banik
Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I3fcd971402e540d91a7392ca58175eb3ecc24cec Reviewed-on: https://review.coreboot.org/c/coreboot/+/45981 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel/common/block/acpi: Factor out common smbus.aslSubrata Banik
This patch moves smbus.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify SBUS device present inside common smbus.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib1ae48f7ece3e521501d92c40cd551287ea2f1ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/45979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/common/block/acpi: Factor out common pch_glan.aslSubrata Banik
This patch moves pch_glan.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify GLAN device present inside common pch_glan.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I479678c864eba39e5ab04f658600e8cba48198ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/45975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel: Make use of PMC low power program from common blockSubrata Banik
List of changes: 1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory 2. Remove redundant PMC programming from SoC and refer to common code block 3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC function. Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel: Move pch_misc_init() to common codeSubrata Banik
List of changes: 1. Move pch_misc_init() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. 3. Create macros for IO port 0x61 and 0x70 as applicable. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel: Move soc_pch_pirq_init() to common codeSubrata Banik
List of changes: 1. Rename soc_pch_pirq_init() as pch_pirq_init() and move into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: I856b5ca024e58fd14b4d1721f23d9516a283ebf8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel: Move pch_enable_ioapic() to common codeSubrata Banik
List of changes: 1. Move pch_enable_ioapic() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-02drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES configShelley Chen
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability. BUG=b:150502246 BRANCH=None TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled). Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-30soc/intel/icelake/acpi/gpio.asl: Correct GADD methodAngel Pons
Some cases are inconsistent. Refer to the 495 series on-package PCH to confirm which GPIO pads are the first for each community and fix it. Change-Id: Ie4c4c12c6629478d754f55fa3fb75fa16eb01335 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-28soc/intel/common/block/lpc: add acpi nameJonathan Zhang
Add ACPI name for LPC device. The name matches with what is in soc/intel/common/block/acpi/acpi/lpc.asl. Since several Intel SOCs select CONFIG_SOC_INTEL_COMMON_BLOCK_LPC, remove duplicated acpi name assignments. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: If418c83caafe5d9e2af135a8946cbe5eb687b9ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/45590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-27soc/intel/icelake/acpi/gpio.asl: Use ASL 2.0 syntaxAngel Pons
While we're at it, fix up cosmetics on a few comments. The GADD method seems to suffer from copy-paste symptoms. A follow-up will address this. Some methods deliberately remain untouched in this commit, so as not to collide with another patch train that already takes care of them. Tested with BUILD_TIMELESS=1, Intel Ice Lake U RVP does not change. Change-Id: I613f5f65638b92ca23f3ce15a15dd063afa52c31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-09-27soc/intel/common/block/acpi: Factor out common gpio_op.aslSubrata Banik
This patch moves gpio_op.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify all methods present inside common gpio_op.asl like GRXS, GTXS etc. are still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I248f5e66994d2f3d6b0bd398347e7cf9ae7f2cc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-27soc/intel/icelake: Use GPIO state macros from intelblocks/gpio_defs.hSubrata Banik
TEST=Able to build and boot ICLRVP platform. 1) Dump and disassemble DSDT to ensure GRXS function implementation remain unchanged prior and after this CL. 2) Verify no ACPI error seen while running 'dmesg' from console. 3) abuild --timeless to ensure there are no other functional changes. Change-Id: Iab4690341bc3da5d8eb249da4d407d84f7d4e706 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45680 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-26arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`Angel Pons
Nearly every x86 platform uses the same arch for all stages. The only exception is Picasso. So, factor out redundant symbols from the rest. Alder Lake is not yet complete, so it has been skipped for now. Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-25soc/intel: Use ASL 2.0 syntax for GPIO ASL helper functionSubrata Banik
Migrate ASL helper function like GRXS, GTXS, STXS, CTXS to ASL 2.0 syntax across CNL, ICL, JSL, SKL. TEST=Able to build and boot Hatch, EVE and ICLRVP platform. Dump and disassemble DSDT to ensure GRXS,GTXS etc functions implementation remain unchanged prior and after this CL. Change-Id: I0ebf1f86031eae25337d2dbeabb8893d9f19a14b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45677 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22Revert "soc/intel: Refactor do_global_reset() function"Furquan Shaikh
This reverts commit 77cc3267fc970c710299a164ecbc471f9287d719. Reason for revert: Breaks quark and also needs breaking down into multiple CLs as commented by Nico on CB:45541 Change-Id: Idf4ca74158df15483856754ee24cc4472a8e09b0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-21src/soc/intel: Drop unneeded empty linesElyes HAOUAS
Change-Id: Id93aab5630e928ee4d7e957801e15a4cc8739fae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44594 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21soc/intel: Refactor do_global_reset() functionSubrata Banik
List of changes: 1. Rename do_global_reset() to force_global_reset() 2. Make force_global_reset() function static 3. Implement force_global_reset() into common/reset.c to avoid dedicated SoC implementation 4. Remove redundant force_global_reset() implementation from dedicated SoC 5. Make direct call to global_reset() from cse_lite.c 7. Drop CONFIG_HAVE_CF9_RESET_PREPARE Kconfig from APL SoC due to common reset (soc/intel/common/reset.c) code migration 8. Remove unused function send_global_reset() from SKL me.c due to common reset code migration 9. Delete heci.c from APL SoC as unused Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I1c5dc8d5606ef28ffaed4a64d90f470ae1ffc2a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-21soc/intel: rename get_prmrr_sizeMichael Niewöhner
get_prmrr_size does not return the actual PRMRR size but a valid PRMRR size with repect to the users choice in Kconfig. Thus, rename it from `get_prmrr_size` to `get_valid_prmrr_size` to avoid confusion about what it does. Also fix the broken comment in cpulib.h. Change-Id: Id243be50acb741f2c3118ddde082743d08983a53 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-19soc/intel/common/block/cse: Refactor cse_request_global_reset() functionSubrata Banik
List of changes: 1. Check if CSE is enabled from devicetree.cb 2. Create helper function cse_request_reset() 3. Modify caller function argument cse_request_global_reset() Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I3668b473bec8d51f847908d11e2e25c485ec7a97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45341 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.hSubrata Banik
Removed unused header files in chip.h Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Idb9b1ed23df3dbb9dad4d36651064c21a4d913fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-14soc/intel/common/cpu: Update COS mask calculation for NEM enhanced modeAamir Bohra
Update the COS mask calculation to accomodate the RW data as per SoC configuration. Currently only one way is allocated for RW data and configured for non-eviction. For earlier platform this served fine, and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a single way. Hence update the number of ways to be configured for non- eviction as per total LLC size. The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/ way size gives the number of ways that need to be configured for non- eviction, instead of harcoding it to 1. TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892) as COS mask selection register and hence needs to be progarmmed accordingly. Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33 of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before MSR write instead of eax(maps 31:0). This implementation corrects that as well. BUG=b:149273819 TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced CAR configuration. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-06soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by defaultMichael Niewöhner
Fsp configures the USB over-current pin and overrides the according pad configuration to NF1, regardless of the port being configured as disabled. Thus, set the OC pin to 0xff ("disabled") in this case to prevent this. This allows us to skip setting USBx_PORT_EMPTY in the devicetree for disabled USB ports. Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45112 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPEAaron Durbin
The wake source macro for GPE events was using 'GPIO'. However, current usage is really all GPEs. Therefore, provide clarity in the naming in order to allow for proper GPIO wake events that are separate from the ACPI GPE block. BUG=b:159947207 Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-09soc/intel/{icl.tgl,jsl}: Remove SMRAM register programmingAamir Bohra
SA SMRAMC register PCI offset 0x88 is deprecated for ICL, JSL and TGL. Removing the register programming for these platforms. The write to this register does not take effect and remains configured to 0, even when programmed. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-07soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASESubrata Banik
In 'bootblock/pch.c', clear PCI_COMMAND_MASTER (BIT 2) prior to programming PWRMBASE and enable BIT 2 after programming PWRMBASE along with PCI_COMMAND_MEMORY (BIT 1). Also perform below operations 1. Use pci_and_config16 instead of pci read and write 2. Use setbits32 instead of mmio read and write Change-Id: I7a148c718d7d2b618ad6e33d6cec11bd0bce0937 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-07src/soc/intel/icelake: Allow option to use USE_INTEL_FSP_MP_INITSubrata Banik
This patch removes the unnecessary enforcement of MP PPI in ICL in order to have parity with other IA-SoC. Now it allows user to select USE_INTEL_FSP_MP_INIT if required. TEST=Able to build and boot ICL platform with either USE_INTEL_FSP_MP_INIT or USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI selected. Change-Id: I25288a24cdf9dceec45a90e4e7233225a6cab508 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-05{nb,soc}/intel: Use get_current_microcode_rev() for ucode versionSubrata Banik
This patch removes all redundant read microcode version implementation from SoC directory and refer from cpu/intel/microcode/microcode.c file. TEST=Able to get correct microcode version. Change-Id: Icb905b18d85f1c5b68fac6905f3c65e95bffa2da Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44175 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-01soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecatedSubrata Banik
FSP default UPD for SkipMpInit is set to 0 which refers to run CPU feature programming on all cores (BSP + APs). Setting SkipMpInit=1 is not recommended as it will only limit CPU feature programming on BSP. TEST=Able to perform CPU feature programming by FSP on all cores using external MP PPI services. Change-Id: I22e70f5f15e53c5fabd78cc3698c4d718b607af6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-26src: Update bare access to BOOL CONFIG_ vals to CONFIG()Martin Roth
BOOL type Kconfig values should be used through the CONFIG() macro. These instances were not, so update them. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26cpu,soc/intel: Drop select SMPKyösti Mälkki
Implicitly selected with MAX_CPUS != 1. Change-Id: I4ac3e30e9f96cd52244b4bae73bafce0564d41e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove unused 'include <cbmem.h>'Elyes HAOUAS
Change-Id: Ib41341b42904dc3050a97b70966dde7e46057d6b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-21src: Use ACPI macrosElyes HAOUAS
Change-Id: I2cf11b784299708f02fd749dcb887b6d25f86f5b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-14src: Remove unused 'include <stdint.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06soc/intel: Drop unused `#include <reg_script.h>`Angel Pons
In some cases, the SoC did not even select `REG_SCRIPT` in Kconfig. Change-Id: I617f332b80c534997e06a91247d1be90a85573be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1Jonathan Zhang
Not all FSPs based on FSP 2.1 supports the feature of external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE. Deselect FSP_PEIM_TO_PEIM_INTERFACE when PLATFORM_USES_FSP2_1 is selected. Update Kconfig of SOCs affected (icelake, jasperlake, tigerlake). Change-Id: I5df03f8bcf15c9e05c9fd904a79f740260a3aed7 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-06-16soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)Kyösti Mälkki
Change-Id: I8c4dc5ab91891de9737189bd7ae86df18d86f758 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16arch/x86: Create helper for APM_CNT SMI triggersKyösti Mälkki
Attempts to write to APM_CNT IO port should always be guarded with a test to verify SMI handler has been installed. Immediate followup removes redundant HAVE_SMI_HANDLER tests. Change-Id: If3fb0f1a8b32076f1d9f3fea9f817dd4b093ad98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41971 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10ACPI: Remove Kconfig COMMON_FADTKyösti Mälkki
Also remove default mb/*/fadt.c from Makefiles. Change-Id: I6a2839c524f8311ec9a382a84066afc7d579eaca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41948 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-03soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: Ibe9752a3f09e8944f7fbcf385b83faae95a7cd9b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-02soc/intel/common/{pch,sata}: Remove SATA common code driverSubrata Banik
Right now all FSP2.0 based IA platform doesn't need this driver anymore hence removing to avoid debug and maintenance effort. TEST=Verified booting from SATA on SPT/CNP/ICP/TGP PCH platforms. Change-Id: Ied3832b26ba1fdd4c30fafe8149689a01d302c3e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41674 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02{icelake,jasperlake,skylake,tigerlake}/bootblock.c: Clean up includesElyes HAOUAS
Drop unused includes and add missing <intelblocks/systemagent.h>. Change-Id: I06c8b2bf65283c3c1fcd25fdaae298b82fc0e09c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-02src: Remove unused '#include <cpu/x86/lapic.h>'Elyes HAOUAS
Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'. Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/common: Improve Type16 SMBIOS tablesPatrick Rudolph
Use CAPID0_A to provide information closer to reality. * Correctly advertise ECC support, max DIMM count and max capacity * CAPID0_A hasn't changed since SNB, but most EDS mark the bits as reserved even though they are still used by FSP. * Assume the same bits for Tiger Lake as for Ice Lake * Assume the same bits for Skylake as for Coffee Lake * Add CAPID0_A to Icelake headers The lastest complete documentation can be found in Document: 341078-002. Change-Id: I0d8fbb512fccbd99a6cfdacadc496d8266ae4cc7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-05-27soc/intel/gma: Implement fsp_soc_get_igd_bar() in common codeNico Huber
`fsp/util.h` draws incompatible UDK headers in. Hence, we have to declare it locally again. Change-Id: Iaa5981088eeb5c36f765d6332ae47a38a6a4c875 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40729 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/intel/gma: Move display and opregion init to common codeNico Huber
Change-Id: I359b529df44db7d63c5a7922cb1ebd8e130d0c43 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40725 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27drivers/intel/gma: Move IGD OpRegion to CBMEMNico Huber
It never was in GNVS, it never belonged among the ACPI tables. Having it in CBMEM, makes it easy to look the location up on resume, and saves us additional boilerplate. TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and intel_backlight + acpi_video synchronize, both before and after suspend. Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20icelake: remove unused processor power limits configurationSumeet R Pawnikar
Remove unused processor power limit configuration parameter and function call based on common code base support for Intel Icelake SoC based platform. BRANCH=None BUG=None TEST=Built for icelake based dragonegg board. Change-Id: Id8923f2c176092b6f7acfbfb079587f88258dce8 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41236 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()Furquan Shaikh
This change uses cpu_phys_address_size() to calculate the size of high MMIO region instead of a macro for each SoC. This ensures that the entire range above TOUUD that can be addressed by the CPU is used for MMIO above 4G boundary. Change-Id: I01a1a86c0c65856f9f35185c2f233c58f18f5dfe Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-14soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4GFurquan Shaikh
This change sets the base for MMIO above 4G to TOUDD. It matches what is used by resource allocator if MMIO resources are allocated above 4G and also matches the expectation in northbridge.asl. This change also gets rid of the macro ABOVE_4GB_MEM_BASE_ADDRESS since it is now unused. BUG=b:149186922 TEST=Verified that kernel does not complain about MMIO windows above 4G. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ibbbfbdad867735a43cf57c256bf206a3f040f383 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41155 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12device/pci_device: Extract pci_domain_set_resources from SOCRaul E Rangel
pci_domain_set_resources is duplicated in all the SOCs. This change promotes the duplicated function. Picasso was adding it again in the northbridge patch. I decided to promote the function instead of duplicating it. BUG=b:147042464 TEST=Build and boot trembyle. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iba9661ac2c3a1803783d5aa32404143c9144aea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08soc/intel: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: I468d2ba85033c41ba53333ebbfd6f4108a36e407 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01src: Remove unused 'include <cpu/x86/cache.h>'Elyes HAOUAS
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/intel: Constify struct device *param to sd_fill_soc_gpio_infoFurquan Shaikh
sd_fill_soc_gpio_info() does not need to modify device structure. Hence, this change makes the struct device * parameter to this function as const. Change-Id: I237ee9640ec64061aa9ed7c65ea21740c40b6ae2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-28device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh
.write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-17soc/intel: Disable config option for SCS by defaultDuncan Laurie
The eMMC/SD interface is not present in all Intel platforms so this change removes the default enable for the storage controller and instead enables it in the specific SoCs that do provide it. Currently this includes all platforms except Tigerlake. Change-Id: I8b6cab41dbd5080f4a7801f01279f47e80ceaefd Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14soc/intel/icelake: Add function to dump ME firmware status informationKrishna Prasad Bhat
Add a function to dump ME Host Firmware Status registers. BUG=None BRANCH=None TEST=Build and boot iclrvp. Change-Id: I9430189665c94decb2e64680d28a7390ee6e912c Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-04-14soc/intel/{icl,tgl}: Make use of print_me_fw_version() from CSE libKrishna Prasad Bhat
Make use of print_me_fw_version() which is defined in the CSE lib to print ME firmware version information for icl,tgl. BUG=None BRANCH=None TEST=Build and boot iclrvp, tglrvp boards. Change-Id: Ief75403c490eee499a84372e54fa38ea3016cc11 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-13acpi: Bump FADT to revision 6Patrick Rudolph
Some of the revision 4 FADT fields were already updated to ACPI spec revision 6, but not all of them. In addition the advertised FADT revision was 3. Implement all fields as defined in version 6 and bump the advertised FADT revision to 6. Also set all used access_size fields and x_gpe0_blk to sane values as Windows 10 verifies those fields starting with FADT revision 5. Fixes: https://ticket.coreboot.org/issues/109 Tested on Windows 10. Change-Id: Ic649040025cd09ed3e490a521439ca4e681afbbf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-10Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber
`.read_resources` and `.set_resources` are the only two device operations that are considered mandatory. Other function pointers can be left NULL. Having dedicated no-op implementations for the two mandatory fields should stop the leaking of no-op pointers to other fields. Change-Id: I6469a7568dc24317c95e238749d878e798b0a362 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06soc/intel/icelake: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1edbc8bb0efaad033385f29f8a4747bd178296b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-05fsp2_0: Gather Kconfig declarationsNico Huber
Move more Kconfig declarations to drivers/intel/fsp2_0/ and document them properly. This way, we don't have to repeat dependencies and have the prompts in a common place. We can also easily hide the prompt for the header path in case the FSP repository is used. SP platforms were skipped as their Kconfig is too weird but they shouldn't hold other platforms back. Change-Id: Iba5af49bcd15427e9eb9b111e6c4cc9bcb7adcae Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30intel/fsp2_0: Make FSP_USE_REPO a SoC opt-inJohanna Schander
For quite a bit now we are extending the FSP_USE_REPO option to be available for all Intel SoCs. This results in a list being not only hard to maintain but also prone to errors. To change that behaviour this commit introduces the HAVE_INTEL_FSP_REPO config option for SoCs that are supported from within 3rdparty/fsp. If a SoC selects HAVE_INTEL_FSP_REPO the config option FSP_USE_REPO is selected by default, but can be still deselected by the user in menuconfig. Change-Id: I68ae373ce591f06073064aa75aac32ceca8fa1cc Signed-off-by: Johanna Schander <coreboot@mimoja.de> Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37582 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30soc/intel/{icelake, tigerlake}: Remove DDI A lane programmingRonak Kanabar
For newer Intel graphics(>=11), The DDI port max lanes are set to 4 by default. And kernel driver no longer relies on coreboot to provide information via DDI_BUF_CTL_A(for DDI port A) register programming. Hence removing this code. BUG=b:150788968 BRANCH=None TEST=checked jslrvp and tglrvp compilation and boot. Change-Id: I32692501b60f48a07b8fbb9bb3a755b18f4b3ea9 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39313 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-15soc/intel/icelake: Re-flow comment for 96 charactersPaul Menzel
Change-Id: I7a5d7bb476c33ab995136eb47ef0258b483a42ef Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-15soc/intel/icelake: Correct past participle in commentPaul Menzel
Change-Id: I117c8d2f71824292c4ca87b6f9434d2106bb512d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-12soc/intel/*/smihandler: Only compile in TCO SMI handler if neededPatrick Georgi
commit 7f9ceef disables TCO SMIs unless specifically enabled, so help the linker throw out the function that handles them in that case. Change-Id: Ia3c93b46e979fb8b99282875b188415f249d38dd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michael Niewöhner
2020-03-10soc/intel: fix eist enablingMatt Delco
There was a bug like this for skylake that seems to have been copied to other SoCs. Signed-off-by: Matt Delco <delco@chromium.org> Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-07intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registersMichael Niewöhner
Add registers that are relevant for the case intrusion detection functionality. Intel documents: 332691-003EN, 335193-006, 341081-001, ... Change-Id: If12d21e8e6721abb877cbbfbbba8f0127a86d96b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-07intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selectedMichael Niewöhner
Enable TCO SMIs in common code, if selected by Kconfig. This is needed for the follow-up commits regarding INTRUDER interrupt. Tested on X11SSM-F. Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-04src: capitalize 'PCIe'Elyes HAOUAS
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-01soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by KconfigSubrata Banik
This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_<SOC>LAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details. TEST=Able to connect ITP/DCI with target system. Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-02-26soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resumeSubrata Banik
This patch makes all legacy 8254 FSP UPDs (Enable8254ClockGating and Enable8254ClockGatingOnS3) depend on CONFIG_USE_LEGACY_8254_TIMER to avoid discrepancy between S0 and S3 resume flow. TEST=Able to boot to TianoCore without any hangs and errors, also verified S3 resume path doesn't clock gate 8254 timer using FSP-S UPD. Change-Id: Id6fe74a51537abbb9ff48db925e37a64e5b21f78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39110 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25soc/intel/common/block: Move cse common functions into block/cseSubrata Banik
This patch cleans soc/intel/{cnl, icl, tgl} by moving common soc code into common/block/cse. Supported SoC can select existing HECI_DISABLE_USING_SMM option to select common cse code block to make heci function disable using sideband interface during SMM mode at preboot envionment. BUG=b:78109109 TEST=Able to make HECI disable in SMM mode successfully without any hang or errors in CNL, ICL and TGL platform. Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26133 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25soc/intel/common/block: Move smihandler common functions into common codeSubrata Banik
This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc code into common/block/smihandler.c BUG=b:78109109 TEST=Build and boot KBL/CNL/APL/ICL/TGL platform. Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-24soc/intel/icelake: Skip FSP-S IGD related UPD overrideSubrata Banik
Default FSP values for "GtFreqMax" and "CdClock" UPDs are "Auto", hence related FSP-S UPD override can be avoided from coreboot. As per FSP-S UPD Header (FspsUpd.h) /** Offset 0x020E - GT Frequency Limit 0xFF: Auto(Default) **/ UINT8 GtFreqMax; /** Offset 0x0209 - CdClock Frequency selection 0: (Default) Auto **/ UINT8 CdClock; TEST=Able to get Pre-OS display on ICLRVP and Dragonegg platform. Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-02-17src/intel: Define HFSTS3 registerSridhar Siricilla
Changes: 1. Define HFSTS3 register across SoCs(apl/cnl/icl/tgl). 2. Define cse_is_hfs3_fw_sku_custom() which checks ME's Firmware SKU is Custom or not. TEST=Verified on hatch, soraka, bobba and iclrvp. Change-Id: I4188e58a4a08d87be2d84674e00ed1407fb8bf82 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-17soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774Wim Vervoorn
Make sure the Skylake comment refers to the correct BWG paragraph and update the text for all. BUG=N/A TEST=build Change-Id: Id383f200e079bdb91cea2240bd7a957d723a7b89 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 15:45:28 +0000