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authorMichael Niewöhner <foss@mniewoehner.de>2020-10-15 00:36:29 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-10-26 06:51:42 +0000
commita64b4f454894988a9c043d53d00b493852f261a3 (patch)
tree44aacf270999724b4461edb3b4c35959482b4330 /src/soc/intel/icelake
parentd5a45470c816bc8a8bdc43951c9e4c4a592b55d3 (diff)
mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/soc/intel/icelake')
-rw-r--r--src/soc/intel/icelake/chip.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index 386e77520a..e1b697e3c7 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -169,8 +169,7 @@ struct soc_intel_icelake_config {
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;
- /* Intel Speed Shift Technology */
- uint8_t speed_shift_enable;
+
/* Enable VR specific mailbox command
* 00b - no VR specific cmd sent
* 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent