coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2016-08-30	fsp_broadwell_de: Refactor code for SPI debug messages	Werner Zeh
2016-08-11	fsp_Broadwell_DE: Do not set IRQ3 and IRQ4 to level	Kevin Paul Herbert
2016-08-03	fsp_broadwell_de: Add DMAR table to ACPI	Werner Zeh
2016-08-01	Remove non-ascii & unprintable characters	Martin Roth
2016-08-01	Add newlines at the end of all coreboot files	Martin Roth
2016-07-31	src/soc: Capitalize CPU, ACPI, RAM and ROM	Elyes HAOUAS
2016-07-15	soc/intel/fsp_broadwell_de: use common Intel ACPI hardware definitions	Aaron Durbin
2016-07-14	fsp_broadwell_de: Add SMBus driver for ramstage	Werner Zeh
2016-07-07	intel/fsp_broadwell_de: Do not use hard coded SCI IRQ for ACPI	Werner Zeh
2016-07-06	PCI: Use PCI_DEVFN macro instead of DEV_FUNC	Werner Zeh
2016-06-30	fsp_broadwell_de: Enable Super I/O address range decode	Werner Zeh
2016-06-29	intel romstage: Use run_ramstage()	Kyösti Mälkki
2016-05-06	soc/intel/fsp_broadwell_de: convert to using common MP init	Aaron Durbin
2016-05-02	cpu/x86/mp_init: remove unused callback arguments	Aaron Durbin
2016-04-20	intel/fsp_broadwell_de: fix SPD CBFS file type	Stef van Os
2016-04-17	broadwell_de_fsp: Select HAVE_INTEL_FIRMWARE	Werner Zeh
2016-04-14	soc/intel: Add Broadwell-DE SoC support	York Yang