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The `limit` field for the PMC fixed BAR was incorrectly set to the `base
+ size + 1`, where it should be `base + size - 1`, to correctly tell the
allocator the limit.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib2d8c7ffe87fdd970f3172bb4e6b2c9386859ab3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65460
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is a lot of going back-and-forth with the KiB arguments, start
the work to migrate away from this.
Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the non-volatile storage as it handles VBNV storage in either
flash or CMOS, is chosen based on board design, removing VBOOT_VBNV_CMOS
& VBOOT_VBNV_CMOS_BACKUP_TO_FLASH from EHL soc kconfig.
Will add the option to EHL CRB mainboard kconfig later.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I97fb7017bff7751d64571d1a8ee7c8b9e2771731
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64473
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch renames heci_init() to cse_init() as HECI initialization
should have a bigger scope than just initializing the CSE
(a.k.a HECI1 alone).
BUG=none
TEST=Able to build and boot google/taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Since of moving RAPL disabling to common code a config switch is
available to select that RAPL disabling has to be done via MCHBAR.
This patch selects the switch for EHL.
Test: Boot mc_ehl1 and ensure that relevant bits in MCHBAR are the same
as before the patch.
Change-Id: I1d0b7f650aa3ccf89c5c35d9b60a83a1ce48c74f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This patch brings the feature of disabling RAPL to common code. It
replaces the current solution for APL and EHL.
For special case if RAPL disabling is only working via changes in MCHBAR
a new config switch was introduced.
Test: Boot mc_apl4/5 with this patch and ensure that the
relevant bits in MSR 0x610 are the same as before the
patch.
Change-Id: I2098ddcd2f19e3ebd87ef00c544e1427674f5e84
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This patch implements a SoC overrides to set CPU privilege level
as the MSR is not consistent across platforms. For example:
On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151.
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This patch provides the possibility for EHL based boards to disable
RAPL settings via SOC_INTEL_DISABLE_POWER_LIMITS config switch.
On Elkhart Lake the way via setting relevant MSR bits does not work.
Therefore the way via MCHBAR is choosen.
Test:
Check MCHBAR mapped registers (MCH_PKG_POWER_LIMIT) on mc_ehl1.
Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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EHL MAC side expects a rising edge signal for an IRQ. Based on the
mainboard wiring it could be necessary to change the interrupt polarity.
This patch provides the functionality to invert a falling edge signal
that comes from an external PHY. The inverting can be activated via
devicetree parameter.
Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Use defines for a better reading of the code.
Change-Id: I8e696240d649c0ea2341b8f04b62eebffebc1d57
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64519
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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By right if PseTsnGbeSgmiiEnable is disable,
PseTsnGbePhyInterfaceType should use RGMII setting.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: If593a5534716a9e93f99cb155fb5e86e12b1df17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Follow this commit 95986169f (soc/intel/alderlake: Skip FSP Notify APIs)
to skip FSP Notify APIs.
Elkhart Lake SoC deselects Kconfigs as below:
- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
to skip FSP notify APIs (Ready to boot and End of Firmware) and make
use of native coreboot driver to perform SoC recommended operations
prior booting to payload/OS.
When deselecting these Kconfigs, cse_final_ready_to_boot() and
cse_final_end_of_firmware() in the common cse driver will be used
instead as required operations to perform prior to booting to OS.
Check out this CL for further info:
commit 90e318bba (soc/intel/common/cse: Add `finalize` operation for
CSE)
Additionally, create a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again config.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I477c204233f83bc96fd5cd39346bff15ed942dc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove two redundant `void *` casts in `clrsetbits32()` calls. In
addition, preemptively retype the `io_mem_base` variable in order
to avoid having to add casts in future commits.
Change-Id: Iae9c8189a6f8cd29181c52c2241789c6d392d77b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Remove devicetree options that aren't used anywhere in the code.
Change-Id: I7eace61079e14423325332d277fdda4f986fd133
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64403
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's
state in the devicetree. This avoids having to manually make sure the
SMBus PCI device and the `SmbusEnable` setting are in sync.
Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch provides the functionality to change the TSN GbE MAC
addresses. Prerequisite for this is a mainboard specific function that
returns a matching MAC address.
A test was performed with the next patch in the series, which enables
the TSN GbE driver for mc_ehl2 mainboard.
Change-Id: I2303a64cfd09fa02734ca9452d26591af2a76221
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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To be able to make EHL Ethernet GbE-TSN Controller configurable, a
driver is required. Functionality comes in following patches.
Change-Id: I7522914c56b74486bb088280d2686acf7027d1d3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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GNVS is more fragile as you need to keep struct elements in sync with
ASL code.
Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size. intel/apl is an exception since the
bootblock size is limited to 32K.
Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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`sa_lockdown_cfg` function ensures locking the PAM register hence,
skip dedicated calling into `sa_lock_pam()` from the SoC
`finalize.c` file. Dropped sa_lock_pam() call from ADL/CNL/EHL/JSL
and TGL.
Additionally, this patch enforces SA lockdown configuration for SKL
and ICL as well.
BUG=b:211954778
TEST=Able to build google/brya with these changes.
> localhost ~ # lspci -xxx | less
00:00.0 Host bridge: Device 8086:4601 (rev 04)
Bit 0 for all PAM registers a.k.a, PAMx_0_0_0_PCI.LOCK bit is set
(meaning locked).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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1. Remove dmi.h as it's migrated as gpmr.header
2. Remove unused gpmr definitions
3. For old platforms, define DMI defintions in c code
for less code changes.
TEST=Build
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch provides the set value for intel speed step in devicetree
for FSPS. Before that in case of not set value in device tree the
default value of disabled was overwritten by default enabled of FSP.
Test: mainboard/siemens/mc_ehl/variants/mc_ehl1
Check status of Bit 16 in MSR 0x1a0 after boot.
Change-Id: I0a5ef4968a27978116c21ce35b3818c6b36e086f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch moves `pmc_clear_pmcon_sts` function into common code and
remove SoC specific instances.
Accessing PMC GEN_PMCON_A register differs between different Intel
chipsets. Typically, there are two possible ways to perform GEN_PMCON_A
register programming (like `pmc_clear_pmcon_sts()`) as:
1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration
register.
2. Using MMIO access when GEN_PMCON_A is a memory mapped register.
SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to
perform GEN_PMCON_A register programming using PMC MMIO.
BUG=b:211954778
TEST=Able to build brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeff Daly <jeffd@silicom-usa.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This fixes building with clang.
Change-Id: If2686b0938d34cd66393eb14205c5c8a5b3ba98b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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coreboot uses port index which is 0 based for all PCIe root ports.
In case of PCIe remapping logic, coreboot reads LCAP register from PCIe
configuration space which contains port number (mostly 1 based). This
assumption might not be true for all the ports in coreboot.
TBT's LCAP registers are returning port index which are based on 2.
coreboot's PCIe remapping logic returns port index based on index 1.
This patch adds variable to pcie_rp_config to pass lcap_port_base to the
pcie remapping function, so coreboot can map any n-based LCAP encoding
to 0-based indexing scheme.
This patch updates correct lcap_port_base variable for all PCIe root
ports for all SOCs, so that function returns correct 0-based index from
LCAP port number.
BUG=b:210933428
BRANCH=None
TEST=Check if code compiles for all ADL boards
Change-Id: I7f9c3c8e753b982e2ede1a41bf87d6355b82da0f
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61936
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000,
so define this once in arch/x86 and include this wherever needed. The
old AMD AGESA code in vendorcode that has its own definition is left
unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common
definition.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_" prefix.
1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
The idea here is to let SoC selects all required FSP configs to execute
FSP Notify Phase APIs unless SoC deselects those configs to run native
coreboot implementation as part of the `.final` ops.
For now all SoC that uses FSP APIs have selected all required configs
to let FSP to execute Notify Phase APIs.
Note: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.
Additionally, fixed SoC configs inclusion order alphabetically.
BUG=b:211954778
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch implements the required operations to perform prior to
booting to OS using coreboot native driver when platform decides
to skip FSP notify APIs, i.e., Ready to Boot and End Of Firmware.
Additionally, move the PMCON status bit clear operation to `.final` ops
to cover any such chances where FSP-S Notify Phase or any other later
boot stage may request a global reset and PMCON status bit remains set.
BUG=b:211954778
TEST=Able to build brya with these changes.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0a0b869849d5d8c76031b8999f3d28817ac69247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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According to the Datasheet Volume 1 (doc #636112, [1]) the PCR port ID
for eSPI is 0x72 (see chapter 25.2.2). Fix it in the header file.
[1]: https://cdrdv2.intel.com/v1/dl/getContent/636112?explicitVersion=true
Test=Read and modify PCR registers of eSPI controller.
Change-Id: I5b07ef0f3a285f981791b1f4b4cdbda98ccf05ad
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61841
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implementation for setup_lapic() did two things -- call
enable_lapic() and virtual_wire_mode_init().
In PARALLEL_MP case enable_lapic() was redundant as it
was already executed prior to initialize_cpu() call.
For the !PARALLEL_MP case enable_lapic() is added to
AP CPUs.
Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Select HECI_DISABLE_USING_SMM config for Elkhart Lake to disable HECI1
device using the SBI msg in SMM.
BUG=none
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4ef7ff7aa234ce411092d70bcb2c9141609be90e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This patch provides the possible options for SoC users to choose the
applicable interface to make HECI1 function disable at pre-boot.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for
disabling heci1 using non-posted sideband write (inside SMM) after
FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for
disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH
onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for
disabling heci1 using private configuration register (PCR) write.
Applicable for SoC platform prior to CNL PCH.
Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the
compilation failure.
Finally, rename heci_disable() function to heci1_disable() to make it
more meaningful.
BUG=none
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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|
This patch drops stale TODO comment about enabling eNEM on EHL.
eNEM is non-POR on the elkhartlake product.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I47fd755dec2324e05e6349e51e15abcf26967604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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The TCO timer is the default watchdog of an x86 host and can reset the
system once it has expired for the second time. There are applications
where this reset is not acceptable while the TCO is used. In these
applications the TCO expire event generates an interrupt and software
takes care. There is a bit in the TCO1_CNT register on Elkhart Lake to
prevent this reset on expiration (called NO_REBOOT, see doc #636722 ).
This bit can either be strapped on hardware or set in this register to
avoid the reset on expiration. While the hardware strap cannot be
overridden in software, the pure software solution is more flexible.
Unfortunately, the location for this bit differs among the different
platforms. This is why it has to be handled on soc level rather than on
TCO common code level.
This commit adds a Kconfig option where NO_REBOOT can be enabled. This
makes it easy to reach this feature over to the mainboard where it can
be selected if needed.
Change-Id: Iaa81bfbe688edd717aa02db86f0a93fecdfcd16b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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Enable PSE GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Add PSE GBE ACPI devices
3. Refactor PCH GBE FSP-S code and merge it together
with PSE GBE code
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If3807ff5a4578be7b2c67064525fa5099950986a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
The Intel® Programmable Services Engine (Intel® PSE) is a
dedicated offload engine for IoT functions powered by an ARM
Cortex-M7 microcontroller. It provides independent, low-DMIPS
computing and low-speed I/Os for IoT applications, plus
dedicated services for real-time computing and time-sensitive
synchronization.
The PSE hosts new functions, including remote out-of-band
device management, network proxy, embedded controller lite
and sensor hub.
This CL enables the user to provide the base address of the
PSE FW blob which will then be loaded by the FSP-S onto the
ARM controller. PSE FW will do the initialization work of
PSE controller and its peripherals. The loading of PSE FW
should have negligible impact on boot time unless PSE
controller could not locate the PSE FW and FSP will attempt to
redo PSE FW loading and wait for PSE handshake until it times
out. Once PSE controller locate the PSE FW, it will do
initialization concurrently by itself with coreboot booting.
It also adds PSE related FSP-S UPD settings which enable the
setup of peripheral ownership (assigned to the PSE or x86
subsystem) and interrupts. These assignments need to take
place at a given point in the boot process and cannot be
changed later.
To verify if PSE FW is loaded properly, the user could enable
PchPseShellEnabled flag and the log will be printed at PSE UART
2.
For further info please refer to doc #611825 (for HW overview)
and #614110 (for PSE EDS).
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
The only option to make HECI1 function disable on Elkhart Lake SoC
platform is using SBI under SMM mode.
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
|
|
This patch implements a SoC overrides to check CPU privilege level
as the MSR is not consistent across platforms.
For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR
0x151.
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Found using:
diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<"
Change-Id: I2ca3a7487cbe75f9bec458f4166378a07b833bb5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Enable CPPC entries generation, needed for Intel SpeedShift.
This can be tested by checking sysfs in Linux:
$ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf
The output should look like this, while the values may differ:
/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1
/sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24
/sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5
...
Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
|
|
Found using following command:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy(\|memmove(\|memset(\|memcmp(\|memchr(\|strdup(\|strconcat(\|strnlen(\|strlen(\|strchr(\|strncpy(\|strcpy(\|strcmp(\|strncmp(\|strspn(\|strcspn(\|strstr(\|strtok_r(\|strtok(\|atol(\|strrchr(\|skip_atoi(\|vsnprintf(\|snprintf(' -- src/)
Change-Id: Iae90ff482f534d8de2a519619c20a019d054e700
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Since TGL `spi_protection_mode` bit replaces the previous
`manufacturing mode` without changing the offset and purpose
of this bit.
This patch renames to `manufacturing mode` aka `mfg_mode` to
maintain the parity with other PCHs as part of IA-common code.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6d00f72ce7b3951120778733066c351986ccf343
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Change-Id: I1d975713129d0a7bce823232d225ed17ee28a04d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
Update SA table as per latest EDS (Doc no: 601458).
Add extra SKUs accordingly.
Signed-off-by: Rick Lee <rick.lee@intel.com>
Change-Id: Ia2bb9e54456dbea634c2b8e192f9fe813b9e6706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
|
|
Disable PSE loading by default. If left enabled (current default),
the EHL coreboot will end up in endless restart loop, due to FSP
unable to locate PSE FW image and trigger global reset.
However disabling this flag (PchPseEnable) will cause the coreboot
to trigger a single reset due to CSE signal (HECI: CSE does not
meet required prerequisites). The reason behind this is that FSP
need to perform static disabling (power gate) to fully shut down
PSE HW, and to do this will need to global reset entire system
including CSE. Then PMC will power gate PSE from the start.
To avoid this behavior, the best way to disable PSE is to disable
via IFWI FIT softstrap (For specific detail can refer to Intel EHL
coreboot MR2 release notes). With this, PMC will power gate PSE
from the first cold boot and system will boot happily without
single reset behavior.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
This patch removes unused header inclusion as <intelblocks/thermal.h>
from several SoC finalize.c files.
Change-Id: Ic9ac0ffb352686af22cc9d11b61f904238eef278
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Technically, it's not depending on the hardware but on the software
(OS/payload), if the PM Timer is optional. OSes with ACPI >= 5.0A
support disabling of the PM Timer, when the respective FADT flag is
unset. Thus, drop this guard.
For platforms without hardware PM Timer (Apollo Lake, Gemini Lake) the
Kconfig `USE_PM_ACPI_TIMER` depends on `!NO_PM_ACPI_TIMER`.
As of this change, new platforms must either implement code for
disabling the hardware PM timer or select `NO_PM_ACPI_TIMER` if no such
is present.
Change-Id: I973ad418ba43cbd80b023abf94d3548edc53a561
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
|
|
With using a Kconfig option to add the x86 LAPIC support code to the
build, there's no need for adding the corresponding directory to subdirs
in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added
(cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding
MTRR code selection patch and having verified that all platforms
added the MTRR code on that patch shows that soc/example/min86 and
soc/intel/quark are the only platforms that don't end up selecting the
LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y
which gets overridden to n in the Kconfig of the two SoCs mentioned
above.
Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
All x86-based CPUs and SoCs in the coreboot tree end up including the
Makefile in cpu/x86/mtrr, so include this directly in the Makefile in
cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new
x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is
selected be default could be added and the new CPU/SoC without MTRR
support can override this option that then will be used in the Makefile
to guard adding the Makefile from the cpu/x86/mtrr sub-directory.
In cpu/intel all models except model 2065X and 206AX are selcted by a
socket and rely on the socket's Makefile.inc to add x86/mtrr to the
subdirs, so those models don't add x86/mtrr themselves. The Intel
Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the
subdirs. The Intel Xeon SP SoC directory contains two sub-folders for
different versions or generations which both add x86/mtrr to the subdirs
in their Makefiles.
Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Since PSE devices could be initialized as either host owned
(PCI devices) or PSE owned (will be hidden from coreboot and
only visible to PSE interface), add all PSE devices in PCI
list header file for future usage.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Iaa40cdcb021d05e50504dd85f94e9c021e284d00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58466
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For coreboot proper, I/O APIC programming is not really required,
except for the APIC ID field. We generally do not guard the related
set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC).
In practice it's something one cannot leave unselected, but maintain
the Kconfig for the time being.
Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Each CPU/SoC checks the return value of the mp_init_with_smm and prints
the same error message if it wasn't successful, so move this check and
printk to mp_init_with_smm. For this the original mp_init_with_smm
function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm
function is created which then calls do_mp_init_with_smm, prints the
error if it didn't return CB_SUCCESS and passes the return value of
do_mp_init_with_smm to its caller.
Since no CPU/SoC code handles a mp_init_with_smm failure apart from
printing a message, also add a comment at the mp_init_with_smm call
sites that the code might want to handle a failure.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Using cb_err as return type clarifies the meaning of the different
return values. This patch also adds the types.h include that provides
the definition of the cb_err enum and checks the return value of
mp_init_with_smm against the enum values instead of either checking if
it's non-zero or less than zero to handle the error case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Return a read-only pointer from the `soc_get_cstate_map()` function.
Also, constify the actual data where applicable.
Change-Id: I7d46f1e373971c789eaf1eb582e9aa2d3f661785
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
A regular assignment works just as well and also allows type-checking.
Change-Id: Id772771f000ba3bad5d4af05f5651c0f0ee43d6d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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Set `EnableTcoTimer=1` in order to keep FSP from
1) enabling ACPI Timer emulation in uCode.
2) disabling the PM ACPI Timer.
Both actions are now done in coreboot.
`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.
Change-Id: I8005daed732c031980ccc379375ff5b09df8dac1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
|
|
Since it's just a one-liner, implement disabling of the ACPI timer in
soc code. This reduces complexity.
Change-Id: I434ea87d00f6e919983d9229f79d4adb352fbf27
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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Move disabling of PM Timer to SoC PMC code.
The original reason for placing that in `finalize` [1] was FSP hanging
due to use of the PM timer without enabling timer emulation first in
coreboot, which was added later [2].
[1] commit 6c1bf27dae (intel/skylake: disable ACPI PM Timer to enable
XTAL OSC shutdown)
[2] commit f004f66ca7 (soc/intel/skylake: Enable ACPI PM timer emulation
on all CPUs)
Change-Id: I354c3aea0c8c1f8ff3d698e0636932b7b76125f7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific
handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in
common code.
Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
P_BLK is legacy and superseded by ACPI _CST. Also, the implementation
for most platforms in soc/intel is broken. Thus, drop it.
For APL the IO redirection is kept since it's used as replacement for
the broken MWAIT instructions.
Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Replace the dt option `PmTimerDisabled` with use of the Kconfig option
`USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer.
A default value representing the prior devicetree value was added to the
boards system76/{lemp10,galp5,darp7}, so this change will not alter
behaviour.
Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add a space before the `*/` C-style comment ending.
Change-Id: Ic8928286c8237808b9e380e4393078792589615d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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These platforms no longer use reg-script. Drop unneeded select.
Change-Id: I8fc4dc29d25dffbf9ed1947d0ff013b2fae0faaf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The current names of the PMC init/enable callbacks are very confusing.
Rename them.
Change-Id: I69f54f3b4e1ea9a9b4fa5c8dd9c0d454d7cd1283
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add NMI_EN and NMI_STS registers, so NMI interrupts can be used.
References:
- XEON-SP: Intel doc# 633935-005 and 547817 rev1.5
- ICL-LP: Intel doc# 341081-002
- TGL-LP: Intel doc# 631120-001
- TGL-H: Intel doc# 636174-002
- JSL: Intel doc# 634545-001
- EHL: Intel doc# 636722-002
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I2621f4495dfd4f95f9774d9081e44c604de830a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lance Zhao
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Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: I95753fa536fae8ca4bb95007419875815c1bcb06
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Migrate the last two platforms to using Kconfig through
`get_valid_prmrr_size()` instead of hardcoded values in the devicetree.
Change-Id: I93aa177f741ca8b2a2d50fae2515606b96784e83
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The pep.asl file is being obsoleted by runtime generation, therefore
switch elkhartlake boards to this method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc`
is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig
option is enabled.
Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and
drop the now-redundant inclusions from platform code. Also, deduplicate
the `UDELAY_TSC` guards.
Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.
Change-Id: Ib6fce70d6b0386906850884880dadbf45597452d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I916f19e022633b316fbc0c6bf38bbd58228412be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move post_codes.h from include/console to
commonlib/include/commonlib/console.
This is because post_codes.h is needed by code from util/
(util/ code in different commit).
Also, it sorts the #include statements in the files that were
modified.
BUG=b:172210863
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Change-Id: Ie48c4b1d01474237d007c47832613cf1d4a86ae1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56403
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way
to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer`
CMOS option to allow enabling and disabling the 8254 timer without
having to rebuild and reflash coreboot. If options are not enabled or
the option is missing in cmos.layout, the Kconfig setting is used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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As EHL UART source clock is 120MHz, update the clock divider
parameters (M & N) to reflect the right value.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I30c21bc4d1ef901a318a12664b61be75c1acf23b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol
more than once. This is done in `src/Kconfig`, along with its prompt.
Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename PMC_EPOC to SOC_INTEL_COMMON_BLOCK_PMC_EPOC to maintain
common naming convention.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If8a264007bbb85a44bbdfa72115eb687c32ec36e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Elkhart Lake provides option to configure FIVR (Fully Integrated
Voltage Regulators) via parameters in FSP-S.
This CL removes fixed FIVR config values and expose these parameters
to the devicetree so that they can be configured on mainboard level
as needed.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.
Change-Id: Ieb8063116bee59f6f6bf1f6b0b2349ce22bd67bd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
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Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically
select the per-stage arch options. Subsequent commits will leverage
this to allow choosing between 32-bit and 64-bit coreboot where all
stages are x86. AMD Picasso and AMD Cezanne are the only exceptions
to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set
the per-stage arch options accordingly.
Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The same pattern appears on all `xdci_can_enable()` call sites. Move the
logic inside the function and take the xDCI devfn as parameter.
Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable PCH GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Use EHL own GBE ACPI instead of common code version due to
different B:D.F from the usual GBE
3. Add kconfig PMC_EPOC to use the PMC XTAL read function
Due to EHL GBE comes with time sensitive networking (TSN)
capability integrated, EHL FSP is using 'PchTsn' instead of the
usual 'PchLan' naming convention across the board.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware,
have platforms select `ARCH_X86` directly instead of through per-stage
Kconfig options, effectively reversing the dependency order.
Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then
casted to a pointer type for use with `read32()` and/or `write32()`. But
since commit b324df6a540d154cc9267c0398654f9142aae052 (arch/x86: Provide
readXp/writeXp helpers in arch/mmio.h), the `read32p()` and `write32p()`
functions live in `arch/mmio.h`. These functions use the `uintptr_t type
for the address parameter instead of a pointer type, and using them with
the `soc_read_pmc_base()` function allows dropping the casts to pointer.
Change-Id: Iaf16e6f23d139e6f79360d9a29576406b7b15b07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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1. Replace pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled() while enabling Thermal config.
2. Remove unused local variable of device structure type (struct device *).
Change-Id: Icc2a44d6d3f1a78bf47354049dd9e2a0ed2282ba
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Use devfn_disable() for disabling a PCI device rather than
using `dev->enabled = 0`.
Also, use is_devfn_enabled() to get the device current state prior
updating the FSP-S UPD for XDCI.
TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI
is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`.
Change-Id: I8ca0813e18da0f95eb9293b6d0bbdf933a1e7039
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55725
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Elkhart Lake provides a feature called "In-Band ECC" which uses a piece
of system DRAM to store the ECC information in. There are a few
parameters in FSP-M to set this feature up as needed.
This patch adds code to expose these parameters to the devicetree so
that they can be configured on mainboard level as needed.
Change-Id: I7a4953d7b35277de01daff04211450e3d1bd8103
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55668
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use FSP_ARRAY_LOAD macro for checking and loading array type
configs into array type UPDs to increase readability.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I2562977e55f8909038697f7e19b82ec6b5e47fae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type (struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled()
call.
TEST=Able to build and boot without any regression seen on EHL.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iadf9145a11f27ff0e182f146b6fe5a01e6cf3ed8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Further add initial Silicon UPD settings for FuSa
(Functional Safety). Disable all by default, due to FSP binary
enable all by default.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I88264ba3e3f9f54ad949c55b230082d1fa289fa4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55342
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Further add initial Silicon UPD settings for thermal and power
management stuffs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I04ded059c36f18925b7a74c934fef2566c3db8fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Fix GPIO_COM2_END from GPIO_RSVD_2 to GPIO_RSVD_12.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I670f4bec8f141da73428010371754746a455df25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55334
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select 'HAVE_INTEL_FSP_REPO' so that the FSP binary from the FSP
repository is used by default. Also, use the FSP headers from the FSP
repository instead.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I0c1bcb07ed0f73e1d5ada5f6f16b84816c4ef3d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55229
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This change drops the following unused lpss functions and related
code:
* soc_lpss_controllers_list
* is_dev_lpss
These functions were added to determine if a controller is LPSS for
performing IRQ configuration. But, these never got used and hence are
being dropped.
Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Further add initial Silicon UPD storage settings:
- SATA
- SD card
- eMMC
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Further add initial Silicon UPD settings for:
- PCIe root ports
- USB
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55034
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Further add initial silicon UPD settings for:
- graphics & display
- chipset lockdown
- PAVP
- legacy timer
- PCH master gating control
- HECI
This CL also enables HECI 1 in devicetree.cb.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Add Silicon upd settings for LPSS (GSPI/UART/I2C).
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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