coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2024-10-07	soc/intel/adl to jsl: Explicitly include static.h for config_of_soc	Nicholas Chin
2024-09-04	soc/intel: Refactor ITSS macros	Subrata Banik
2024-01-31	include/device/device.h: Remove CHIP_NAME() macro	Nicholas Sudsgaard
2024-01-17	soc/intel/elkhartlake: Drop redundant PcieRpEnable	Nico Huber
2023-10-20	device/device.h: Rename pci_domain_scan_bus	Arthur Heymans
2023-01-18	soc/intel/elkhartlake: Use common gpio.h include	Dinesh Gehlot
2022-05-16	soc/intel/*: Use SSDT to pass A4GB and A4GS	Arthur Heymans
2022-02-25	intelblocks/pcie: Correct mapping between LCAP port and coreboot index	MAULIK V VAGHELA
2022-01-25	soc/intel/elkhartlake: Add PSE TSN support	Lean Sheng Tan
2021-04-21	soc/intel: Replace open-coded buffer length calculation	Angel Pons
2021-04-21	soc/intel: Fix typo in comment	Angel Pons
2021-03-27	soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h	Subrata Banik
2021-02-24	soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore	Aamir Bohra
2021-02-09	soc/amd,intel: Drop s3_resume parameter on FSP-S functions	Kyösti Mälkki
2020-12-30	soc/intel: hook up new gpio device in the soc chips	Michael Niewöhner
2020-12-14	soc/intel/elkhartlake: Update PCI device definition	Tan, Lean Sheng
2020-09-28	soc/intel/common/block/lpc: add acpi name	Jonathan Zhang
2020-09-08	soc/intel/elkhartlake: Do initial SoC commit till ramstage	Tan, Lean Sheng