| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-10-27 | FSP 1.1: Move common FSP code | Lee Leahy |
| 2015-10-11 | intel fsp1_1: prepare for romstage vboot verification split | Aaron Durbin |
| 2015-10-11 | soc/intel/common: remove chipset specific calls | Aaron Durbin |
| 2015-10-11 | intel SOC common: Remove unused parameters | Lee Leahy |
| 2015-10-11 | intel: update common and FSP cache-as-ram parameters | Aaron Durbin |
| 2015-09-10 | fsp1_1: provide binding to UEFI version | Aaron Durbin |
| 2015-08-29 | fsp raminit: Add romstage_params to soc_memory_init_params | Duncan Laurie |
| 2015-07-23 | intel: common: Let mainboard supplement FSP memory info | Duncan Laurie |
| 2015-06-26 | soc/intel/common: Restrict common romstage/ramstage code to FSP | Lee Leahy |
| 2015-06-24 | Intel/common: Remove copyright address | Lee Leahy |
| 2015-06-24 | Intel Common SOC: Add romstage support | Lee Leahy |
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index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |