| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-02-20 | src/soc: Fix various typos | Jonathan Neuschäfer |
| 2018-02-07 | soc/intel/skylake: Add Kabylake PCH H device ID's | V Sowmya |
| 2018-01-25 | soc/intel/skylake: Clean up the skylake PCH H device ID macros | V Sowmya |
| 2017-12-13 | soc/intel/common/block: Add option to have subsystem_id in common pci driver | Subrata Banik |
| 2017-08-10 | soc/intel/common/uart: Add support for enabling UART debug controller on resume | Furquan Shaikh |
| 2017-08-10 | soc/intel/common/uart: Refactor uart_common_init | Furquan Shaikh |
| 2017-08-04 | soc/intel/common: Add Cannonlake pci ids for common | Lijian Zhao |
| 2017-07-24 | Update files with no newline at the end | Martin Roth |
| 2017-05-22 | soc/intel/common/block/uart: Add GLK UART pci ids | Hannah Williams |
| 2017-05-09 | soc/intel/common: Add PCI configuration code for UART | Aamir Bohra |
| 2017-04-11 | soc/intel/common/block: Add Intel common UART code | Aamir Bohra |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |