coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-08-05	soc/intel/common: Include Alder Lake device IDs	Subrata Banik
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-02-25	soc/intel/common: Update Jasper Lake Device IDs	Meera Ravindranath
2020-01-22	soc/intel/common: Add Elkhartlake Device IDs	Tan, Lean Sheng
2019-12-13	soc/intel/common: Add PCI device IDs for CMP-H	Gaggery Tsai
2019-12-10	soc/intel/common: Add Jasperlake Device IDs	rkanabar
2019-11-05	soc/intel/common: Include Tigerlake device IDs	Ravi Sarawadi
2019-02-26	soc/intel/common: Include cometlake PCH IDs	Ronak Kanabar
2018-11-07	soc/intel/common: Include Icelake device IDs	Aamir Bohra
2018-10-08	Move compiler.h to commonlib	Nico Huber
2018-04-24	compiler.h: add __weak macro	Aaron Durbin
2017-12-13	soc/intel/common/block: Add option to have subsystem_id in common pci driver	Subrata Banik
2017-11-30	soc/intel/common: Add Intel SRAM common code support	V Sowmya