coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-01	soc/intel/common: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-04-06	soc/intel/common: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-02-25	soc/intel/common: Update Jasper Lake Device IDs	Meera Ravindranath
2020-01-22	soc/intel/common: Add Elkhartlake Device IDs	Tan, Lean Sheng
2019-12-13	soc/intel/common: Add PCI device IDs for CMP-H	Gaggery Tsai
2019-12-10	soc/intel/common: Add Jasperlake Device IDs	rkanabar
2019-11-05	soc/intel/common: Include Tigerlake device IDs	Ravi Sarawadi
2019-09-06	soc/intel/skylake: Add Lewisburg family PCH support	Maxim Polyakov
2019-07-06	soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width	Subrata Banik
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-04	device/mmio.h: Add include file for MMIO ops	Kyösti Mälkki
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2019-02-26	soc/intel/common: Include cometlake PCH IDs	Ronak Kanabar
2019-01-23	soc/{amd,intel}: Remove needless '&' on function pointers	Elyes HAOUAS
2018-11-07	soc/intel/common: Include Icelake device IDs	Aamir Bohra
2018-08-10	src/soc/intel: Add new device IDs to support coffeelake	Maulik
2018-02-07	soc/intel/common/block: Fix SATA chipset register definitions anomalies	Subrata Banik
2017-12-13	soc/intel/common/block: Add option to have subsystem_id in common pci driver	Subrata Banik
2017-10-12	soc/intel/skylake: Enable bus master for sata	Kane Chen
2017-08-04	soc/intel/common: Add Cannonlake pci ids for common	Lijian Zhao
2017-07-24	Fix files with multiple newlines at the end.	Martin Roth
2017-05-22	soc/intel/common: Add Intel SATA common code support	Aamir Bohra