coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-09-06	soc/intel/skylake: Add Lewisburg family PCH support	Maxim Polyakov
2019-03-27	device/pciexp_device: Convert LTR non-snoop/snoop value into common macro	Subrata Banik
2019-03-21	{northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()	Subrata Banik
2019-03-19	Fix 'unsigned int' to bare use of 'unsigned'	Subrata Banik
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-02-26	soc/intel/common: Include cometlake PCH IDs	Ronak Kanabar
2018-11-19	soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature	Subrata Banik
2018-11-07	soc/intel/common: Include Icelake device IDs	Aamir Bohra
2018-10-17	soc/intel/cannonlake: Add new cannon lake PCH-H support	praveen hodagatta pranesh
2018-09-18	soc/intel/common/block: Don't use device_t in ramstage	Elyes HAOUAS
2018-04-20	pci: Move inline PCI functions to pci_ops.h	Patrick Rudolph
2017-12-13	soc/intel/common/block: Add option to have subsystem_id in common pci driver	Subrata Banik
2017-08-04	soc/intel/common: Add Cannonlake pci ids for common	Lijian Zhao
2017-05-22	soc/intel/common: Add Intel PCIe common code	Aamir Bohra