| Age | Commit message (Expand) | Author |
|---|
| 2023-02-01 | treewide: Remove duplicated include <device/pci.h> | Elyes Haouas |
| 2022-10-25 | soc/intel/common: Clean up includes | Elyes Haouas |
| 2022-09-15 | soc/intel/skylake: Assign device ops in chipset devicetree | Nico Huber |
| 2022-05-16 | soc/intel: Add Raptor Lake device IDs | Bora Guvendik |
| 2022-03-09 | soc/intel/common: Include Meteor Lake device IDs | Wonkyu Kim |
| 2022-03-07 | src: Make PCI ID define names shorter | Felix Singer |
| 2022-02-11 | soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N | Usha P |
| 2022-01-25 | soc/intel/common: Include Alder Lake-N device IDs | Usha P |
| 2021-11-12 | soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDs | Tracy Wu |
| 2021-08-19 | soc/intel/common: Add TGL-H PCI IDs | Jeremy Soller |
| 2021-04-28 | soc/intel: Rename 200-series PCH device IDs | Angel Pons |
| 2021-03-15 | pciexp_device: Rewrite LTR configuration | Nico Huber |
| 2021-03-12 | device: Give `pci_ops.set_L1_ss_latency` a proper name | Nico Huber |
| 2021-01-22 | soc/intel/commmon: Include Alder Lake device IDs | Varshit Pandya |
| 2020-08-05 | soc/intel/common: Include Alder Lake device IDs | Subrata Banik |
| 2020-07-28 | src: Never set ISA Enable on PCI bridges | Angel Pons |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-04-06 | soc/intel/common: Use SPDX for GPL-2.0-only files | Angel Pons |
| 2020-03-18 | soc: Remove copyright notices | Patrick Georgi |
| 2020-02-25 | soc/intel/common: Update Jasper Lake Device IDs | Meera Ravindranath |
| 2020-01-22 | soc/intel/common: Add Elkhartlake Device IDs | Tan, Lean Sheng |
| 2019-12-13 | soc/intel/common: Add PCI device IDs for CMP-H | Gaggery Tsai |
| 2019-12-10 | soc/intel/common: Add Jasperlake Device IDs | rkanabar |
| 2019-11-05 | soc/intel/common: Include Tigerlake device IDs | Ravi Sarawadi |
| 2019-10-01 | intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL | Kyösti Mälkki |
| 2019-09-06 | soc/intel/skylake: Add Lewisburg family PCH support | Maxim Polyakov |
| 2019-03-27 | device/pciexp_device: Convert LTR non-snoop/snoop value into common macro | Subrata Banik |
| 2019-03-21 | {northbridge, soc, southbridge}/intel: Make use of generic set_subsystem() | Subrata Banik |
| 2019-03-19 | Fix 'unsigned int' to bare use of 'unsigned' | Subrata Banik |
| 2019-03-08 | coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) | Julius Werner |
| 2019-02-26 | soc/intel/common: Include cometlake PCH IDs | Ronak Kanabar |
| 2018-11-07 | soc/intel/common: Include Icelake device IDs | Aamir Bohra |
| 2018-10-17 | soc/intel/cannonlake: Add new cannon lake PCH-H support | praveen hodagatta pranesh |
| 2018-09-18 | soc/intel/common/block: Don't use device_t in ramstage | Elyes HAOUAS |
| 2018-04-20 | pci: Move inline PCI functions to pci_ops.h | Patrick Rudolph |
| 2017-12-13 | soc/intel/common/block: Add option to have subsystem_id in common pci driver | Subrata Banik |
| 2017-08-04 | soc/intel/common: Add Cannonlake pci ids for common | Lijian Zhao |
| 2017-05-22 | soc/intel/common: Add Intel PCIe common code | Aamir Bohra |
