coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-08-28	soc/intel/cnl: Add CML IGD IDs	Meera Ravindranath
2019-07-30	soc/intel/cannonlake: Add new PCI IDs	Felix Singer
2019-07-21	soc/intel: Expand SA_DEV_ROOT for ramstage	Kyösti Mälkki
2019-07-17	soc/intel/cannonlake: Add device Ids for new CFL SKUs support	Lean Sheng Tan
2019-07-12	soc/intel/common: Add Coffee Lake H 6+2 Xeon graphics id	Nico Huber
2019-06-16	soc/intel/common: Fix booting issue without default IGD enabled	Subrata Banik
2019-06-09	soc/intel/common: Skip SoC GT programming based on CONFIG_SKIP_GRAPHICS_ENABLING	Subrata Banik
2019-05-22	post_code: add post code for hardware initialization failure	Keith Short
2019-03-06	soc/intel/skylake: Add new Northbridge and IGD IDs	Maxim Polyakov
2019-03-04	device/mmio.h: Add include file for MMIO ops	Kyösti Mälkki
2019-02-24	soc/intel/common: Include cometlake SA IDs	Ronak Kanabar
2019-02-19	soc/intel/common: Add whiskeylake celeron v-0 support	Lijian Zhao
2018-11-07	soc/intel/common: Include Icelake device IDs	Aamir Bohra
2018-10-17	soc/intel/cannonlake: Add new cannon lake PCH-H support	praveen hodagatta pranesh
2018-10-08	Move compiler.h to commonlib	Nico Huber
2018-08-20	intel/common/block: Fix issues found by klockwork	John Zhao
2018-08-06	src/soc/intel: Add AML IGD in platform reporting	Gaggery Tsai
2018-08-01	soc/intel/common/block: Add WhiskeyLake (WHL) IDs	Krzysztof Sywula
2018-05-05	soc/intel: Add KBL-R pci id support	Lijian Zhao
2018-04-24	compiler.h: add __weak macro	Aaron Durbin
2018-02-20	src/soc: Fix various typos	Jonathan Neuschäfer
2018-02-07	soc/intel/skylake: Add Kabylake PCH H device ID's	V Sowmya
2017-12-13	soc/intel/common/block: Add option to have subsystem_id in common pci driver	Subrata Banik
2017-12-07	soc/intel/common/block: Add Intel common Graphics controller support	Subrata Banik