summaryrefslogtreecommitdiff
path: root/src/soc/intel/common/block/cpu/car
AgeCommit message (Expand)Author
2022-09-06src: remove force-included header rules.h from individual filesMartin Roth
2022-07-09*/fsp/exit_car: Push stack address into %espArthur Heymans
2022-04-01arch/x86/postcar: Use a separate stack for C executionArthur Heymans
2021-12-13soc/intel/common/block/cpu/car/exit_car_fsp.S: Align stackArthur Heymans
2021-11-18drivers/fsp: Rewrite post code hex values in lowercaseSean Rhodes
2021-10-05src/soc to src/superio: Fix spelling errorsMartin Roth
2021-08-16soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS KconfigSubrata Banik
2021-08-15soc/intel/common: Calculate and configure SF Mask 1Subrata Banik
2021-08-15soc/intel/common: Calculate and configure SF Mask 2Subrata Banik
2021-07-24soc/intel/common/block: Add space before comment delimiterSubrata Banik
2021-07-14soc/intel/common: Use SPR for backing up data way and eviction maskSubrata Banik
2021-06-26soc/intel/cache_as_ram.S: Fix CAR issues with BootguardArthur Heymans
2021-06-24soc/intel/cache_as_ram.S: Fix SOC_INTEL_APOLLOLAKEArthur Heymans
2021-06-24soc/intel/cache_as_ram.S: Add macro to detect bootguard nemArthur Heymans
2021-06-22soc/intel/car: Add support for bootguard CARArthur Heymans
2021-06-22soc/intel/common/cache_as_ram.S: Add macro to clear CARArthur Heymans
2021-06-22soc/intel/common/cache_as_ram.S: Add macro to find a free MTRRArthur Heymans
2021-06-18soc/intel/car/cache_as_ram.S: Fix typo in commentArthur Heymans
2021-05-05drivers/intel/fsp2_0: Fix the FSP-T positionArthur Heymans
2021-03-11soc/intel/common/block/cpu: Use tab instead of spaceSubrata Banik
2021-03-05soc/intel/common/block/cpu: Use tab instead of spaceSubrata Banik
2021-01-07arch/x86: Move prologue to .init sectionKyösti Mälkki
2020-12-14src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGLShreesh Chhabbi
2020-12-14soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config optionShreesh Chhabbi
2020-12-08soc/intel/common/block/cpu/car: Fix two whitespace issuesSubrata Banik
2020-12-01soc/intel/common/block/cpu/car/exit_car: Fix compilation on x86_64Patrick Rudolph
2020-12-01soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 supportPatrick Rudolph
2020-11-02soc/intel/fsp-car: Use the coreboot defined stackArthur Heymans
2020-11-02drivers/intel/fsp2_0: Add function to report FSP-T outputArthur Heymans
2020-09-14soc/intel/common/cpu: Update COS mask calculation for NEM enhanced modeAamir Bohra
2020-06-06src: Remove unused 'include <cpu/x86/mtrr.h>'Elyes HAOUAS
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
2020-05-01src: Remove unused 'include <cpu/x86/cache.h>'Elyes HAOUAS
2020-04-06soc/intel/common: Use SPDX for GPL-2.0-only filesAngel Pons
2020-03-18soc: Remove copyright noticesPatrick Georgi
2019-11-15soc/intel/common: Make alignment proper for commentsSubrata Banik
2019-11-12arch/x86/car.ld: Rename suffix _start/_endArthur Heymans
2019-09-11arch/x86: Restrict use of _car_global[start|end]Kyösti Mälkki
2019-08-12soc/intel/common: Fix typo mistake in cache_as_ram.SSubrata Banik
2019-04-21cpu/x86: Move checking for MTRR's as a proxy for proper CPU resetArthur Heymans
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-01-08arch/x86: Link walkcbfs.S instead of including itArthur Heymans
2018-10-25soc/intel: Consolidate FSP CAR setup and teardown codePraveen hodagatta pranesh
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
2018-06-04src/soc: Get rid of whitespace before tabElyes HAOUAS
2018-04-25soc/intel/common: disable paging if PAGING_IN_CACHE_AS_RAM enabledAaron Durbin
2018-02-20src/soc: Fix various typosJonathan Neuschäfer
2017-10-16intel/common: CAR setup CQOSNaresh G Solanki
2017-06-29arch/x86: update assembly to ensure 16-byte alignment into CAaron Durbin
2017-03-28soc/intel/common/block: Add cache as ram init and teardown codeSubrata Banik