| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-02-01 | drivers/intel/fsp2_0: Use coreboot postcar with FSP-T | Arthur Heymans |
| 2020-10-28 | soc/intel: deduplicate ACPI timer emulation | Michael Niewöhner |
| 2019-11-06 | soc/intel/common: Make native and FSP-T CAR init mutually exclusive | Arthur Heymans |
| 2019-11-05 | soc/intel/common: Don't link CAR teardown in romstage | Arthur Heymans |
| 2019-11-04 | soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig | Michael Niewöhner |
| 2019-04-21 | cpu/x86: Move checking for MTRR's as a proxy for proper CPU reset | Arthur Heymans |
| 2018-10-25 | soc/intel: Consolidate FSP CAR setup and teardown code | Praveen hodagatta pranesh |
| 2017-06-23 | soc/intel/common/block: Add common MP Init code | Barnali Sarkar |
| 2017-06-09 | soc/intel/common/block: Add Intel common CPU library code | Barnali Sarkar |
| 2017-03-28 | soc/intel/common/block: Add cache as ram init and teardown code | Subrata Banik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |