coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2023-03-23	soc/intel: Rename IA common code module from `TOM` to `RAMTOP`	Subrata Banik
2023-03-13	soc/intel/cmn/tom: Cache TOM region early	Subrata Banik
2022-11-21	soc/intel/common: Add support to read CPU and PCH Trace Hub modes	Sridhar Siricilla
2022-10-31	soc: Add SPDX license headers to Makefiles	Martin Roth
2022-10-29	soc/intel/common: Fix potential NULL pointer dereference	Shaik Shahina
2022-06-30	soc/intel/common: Compile debug_feature in ramstage to fix build error	Krishna P Bhat D
2022-06-17	soc/intel/{alderlake, common}: Rename the pre_mem_ft structure	Sridhar Siricilla
2022-05-28	soc/intel/common: Use coreboot error codes	Sridhar Siricilla
2022-04-25	soc/intel/common: Add support to control CSE firmware update	Sridhar Siricilla
2022-04-25	soc/intel/common: Fix buggy code tries to access DESC region	Sridhar Siricilla
2022-04-06	soc/intel/common: Add support to control coreboot and Intel SoC features	Sridhar Siricilla
2020-12-28	kconfig: remove non-existent source	Jack Rosenthal
2020-09-21	soc/intel/common: Keep common non-IP code block inside basecode	Subrata Banik
2018-06-21	soc/intel/common: Make infrastructure ready for Intel common stage files	Subrata Banik