| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-12-09 | soc/intel/cannonlake: Clean up UART code | Aamir Bohra |
| 2017-09-13 | soc/intel/cannonlake: Add ramstage uart debug support | Lijian Zhao |
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index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |