| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-04-29 | soc/intel: Add GPI interrupt config register offset info | Karthikeyan Ramasubramanian |
| 2019-03-04 | soc/intel/cannonlake: Move common definitions to a header file | Rizwan Qureshi |
| 2019-02-27 | soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffers | Rizwan Qureshi |
| 2019-02-22 | soc/intel/cannonlake: Add ASL function for setting pad mode | Rizwan Qureshi |
| 2019-01-03 | soc/intel/cannonlake: Add cannonlake ACPI GPIO op | Lijian Zhao |
| 2018-10-17 | soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions | praveen hodagatta pranesh |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |